SGLS164A April   2003  – October 2024 UC2842AQ , UC2843AQ , UC2845AQ

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Electrical Characteristics
    4. 5.4 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
  9. 8 Application and Implementation
    1. 8.1 Application Information
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.3 Electrical Characteristics

TA = –40°C to 125°C, VCC = 15 V ((1)), RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Output voltage TJ = 25°C, IO = 1 mA 4.95 5.0 5.05 V
Line regulation voltage VIN = 12 V to 25 V 6 20 mV
Load regulation voltage IO = 1 mA to 20 mA 6 25 mV
Temperature stability See Notes 2 and 3 0.2 0.4 mV/°C
Total output variation voltage Line, Load, Temp. 4.9 5.1 V
Output noise voltage f = 10 Hz to 10 kHz, (2)TJ = 25 C 50 μV
Long term stability 1000 hours, (2) TA=125°C 5 25 mV
Output short-circuit current -30 -100 -180 mA
Oscillator Section
Initial accuracy See (4) TJ = 25 C 47 52 57 kHz
Voltage stability VCC = 12 V to 25 V 0.2 1 %
Temperature stability TA = MIN to MAX, (2) 5 %
Amplitude peak-to-peak V pin 7, (2) 1.7 V
Discharge current TJ = 25 C 7.8 8.3 8.8
V pin 7 = 2 V,(3) TJ = Full range 7.5 8.8 mA
Error Amplifier Section
Input voltage COMP = 2.5 V 2.45 2.5 2.55 V
Input bias current -0.3 -1 μA
Open loop voltage gain (AVOL) VO = 2 V to 4 V 65 90 dB
Unity gain bandwidth TJ = 25°C(2) 0.7 1 MHz
PSRR VCC = 12 V to 25 V 60 70 dB
Output sink current FB = 2.7 V, COMP = 1.1 V 2 6 mA
Output source current FB = 2.3 V, COMP = 5 V -0.5 -0.8 mA
VOUT high FB = 2.3 V, RL = 15 kΩ to GND 5 6 V
VOUT low FB = 2.7 V, RL = 15 kΩ to VREF 0.7 1.1 V
Current Sense Section
Gain (3) and (4) 2.85 3 3.15 V/V
Maximum input signal COMP = 5 V, (3) 0.9 1 1.1 V
PSRR VCC = 12 V to 25 V, (3) 70 dB
Input bias current —2 —10 μA
Delay to output ISENSE = 0 V to 2 V, (2) 150 300 ns
Output Section (OUT)
Low-level output voltage IOUT = 20 mA 0.1 0.4 V
IOUT = 200 mA 1.5 2.2
High-level output voltage IOUT = -20 mA 13 13.5 V
IOUT = -200 mA 12 13.5
Rise time CL = 1 nF, (2)TJ = 25 C 25 150 ns
Fall time CL = 1 nF, (2)TJ = 25 C 25 150 ns
UVLO saturation VCC = 5 V, IOUT = 10 mA 0.7 1.2 V
Undervoltage Lockout Section
Start threshold UC2842A, UC2844A 15 16 17 V
UC2843A, UC2845A 7.8 8.4 9
Minimum operation voltage after turn on UC2842A, UC2844A 9 10 11 V
UC2843A, UC2845A 7 7.6 8.2
PWM Section
Maximum duty cycle UC2842A, UC2843A 92 96 100 %
UC2844A, UC2845A 46 48 50
Minimum duty cycle 0 %
Total Standby Current
Start-up current 0.3 0.5 mA
Operating supply current FB = 0 V, SENSE = 0 V 11 17 mA
VCC internal Zener voltage ICC = 25 mA 30 39 V
(1) Adjust VCC above the start threshold before setting at 15 V.
(2) Not production tested.
(3) Parameter measured at trip point of latch with VFB at 0 V.
(4) Gain is defined by: UC2842AQ UC2843AQ UC2844AQ UC2845AQ ; 0 v VSENSE v 0.8 V.