SLAA558A November   2012  – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

 

  1.   Designing With MSP430F522x and MSP430F521x Devices
    1.     Trademarks
    2. 1 Split-Supply I/O Systems
    3. 2 DVIO Supplied I/Os
    4. 3 Secondary Digital Functions on DVIO Supplied I/Os
    5. 4 Split-Supply Power-Up or Power-Down Sequence
    6. 5 Reset and NMI Pin Functionality
    7. 6 XT1 and XT2 Oscillators in Bypass Mode
    8. 7 Bootloader (BSL)
      1. 7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
      2. 7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
    9. 8 Debugger Connections
      1. 8.1 JTAG Standard Interface
      2. 8.2 Spy-Bi-Wire Interface
      3. 8.3 Debugging Without DVIO
    10. 9 References
  2.   Revision History

3 Secondary Digital Functions on DVIO Supplied I/Os

The DVIO supplied general-purpose I/Os are multiplexed with other digital functions in the device, and these digital functions’ I/O circuits are also powered from DVIO. On the F522x and F521x devices, some of the secondary digital functions that are shared with the DVIO supplied I/Os include timer capture compare functions, serial communication functions (USCI UART, SPI, or I2C), comparator output, SMCLK output, and MCLK output. See the signal descriptions table in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers for details.

On the F522x and F521x devices, Port 4 supports port mapping and resides on the DVIO supply domain. Any of the secondary digital functions specified in the port mapping table can be mapped to Port4, and their respective I/O circuitry is supplied by DVIO. See the port mapping table in the Peripherals section of the data sheet for details.

NOTE

In split supply I/O systems, if external pullup resistors are connected to any of the DVIO supplied pins (for example, the USCI I2C pins – SDA and SCL), tie the external pullups to the DVIO supply and not to DVCC.

Other DVIO supplied digital pins on the F522x and F521x devices include:

  • BSLEN – BSL enable pin used by the DVIO supplied BSL interface (see Section 7). By default, this pin has a nonconfigurable internal pulldown resistor enabled.
  • RST/NMI – DVIO supplied reset pin multiplexed with NMI functionality. See Section 5 for details of the reset functionality.