SLAA649G October   2014  – August 2021 MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2013-EP , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2254 , MSP430F2272 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F249-EP , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430F2619S-HT , MSP430FR2032 , MSP430FR2033 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2230-EP , MSP430G2231 , MSP430G2231-EP , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2302-EP , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2332-EP , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430I2020 , MSP430I2021 , MSP430I2030 , MSP430I2031 , MSP430I2040 , MSP430I2041

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Comparison of MSP430FR4xx and MSP430FR2xx Devices
  4. 3 In-System Programming of Nonvolatile Memory
    1. 3.1 Ferroelectric RAM (FRAM) Overview
    2. 3.2 FRAM Cell
    3. 3.3 Protecting FRAM Using the Memory Write Protection Bit
    4. 3.4 FRAM Memory Wait States
    5. 3.5 Bootloader (BSL)
    6. 3.6 JTAG and Security
    7. 3.7 Production Programming
  5. 4 Hardware Migration Considerations
  6. 5 Device Calibration Information
  7. 6 Important Device Specifications
  8. 7 Core Architecture Considerations
    1. 7.1 Power Management Module (PMM)
      1. 7.1.1 Core LDO and LPM3.5 LDO
      2. 7.1.2 SVS
      3. 7.1.3 VREF
      4. 7.1.4 Debug in Low-Power Mode
    2. 7.2 Clock System
      1. 7.2.1 DCO Frequencies
      2. 7.2.2 FLL, REFO, and DCO Tap
      3. 7.2.3 FRAM Access at 16 MHz, ADC Clock, and Clocks-on-Demand
    3. 7.3 Operating Modes, Wake-up Times, and Reset
      1. 7.3.1 LPMx.5
      2. 7.3.2 Reset
        1. 7.3.2.1 Behavior of POR and BOR
        2. 7.3.2.2 Reset Generation
        3. 7.3.2.3 Determining the Cause of Reset
    4. 7.4 Interrupt Vectors
    5. 7.5 FRAM and the FRAM Controller
      1. 7.5.1 Flash and FRAM Overview Comparison
      2. 7.5.2 Cache Architecture
  9. 8 Peripheral Considerations
    1. 8.1  Watchdog Timer
    2. 8.2  Ports
      1. 8.2.1 Digital Input/Output
      2. 8.2.2 Capacitive Touch I/O
    3. 8.3  Analog-to-Digital Converters
      1. 8.3.1 ADC10 to ADC
    4. 8.4  Communication Modules
      1. 8.4.1 USI to eUSCI
      2. 8.4.2 USCI to eUSCI
    5. 8.5  Timer and IR Modulation Logic
    6. 8.6  Backup Memory
    7. 8.7  Hardware Multiplier (MPY32)
    8. 8.8  RTC Counter
    9. 8.9  Interrupt Compare Controller (ICC)
    10. 8.10 LCD
    11. 8.11 Smart Analog Combo (SAC)
    12. 8.12 Comparator
  10. 9 ROM Libraries
  11. 10Conclusion
  12. 11References
  13. 12Revision History

7.2.3 FRAM Access at 16 MHz, ADC Clock, and Clocks-on-Demand

While the FR4xx can source MCLK at 16 MHz, FRAM access is limited to 8 MHz by the FRAM controller, and wait states are required when MCLK is greater than 8 MHz. For configuring wait states, see Section 3.4. Code execution from RAM and accesses to peripherals can be carried out at 16 MHz.

The ADC module's internal oscillator on the F2xx family has been renamed to MODOSC in the FR4xx family (similar to the F5xx family).

The FR4xx CS supports the 'clocks-on-demand' feature. In the F2xx family, the availability of a system clock is affected by entry into a low-power mode. For example, SMCLK is turned off in LPM3 and, hence, any peripheral such as a timer that uses SMCLK is inactive in LPM3. The FR4xx, however, allows the LPM settings to be overridden by a clock request. As long as there is an active request for a clock from a peripheral, the clock remains on, regardless of the LPM setting. This is most easily seen when there is increased power consumption when porting code between families. It is left to the user to disable any modules that request the clock source and prevent the device from entering the required LPM. As an option, this feature can be disabled using the Clock System Control 8 (CSCTL8) register bits MODOSCREQEN, SMCLKREQEN, MCLKREQEN, and ACLKREQEN.

Table 7-1 lists important differences between the clock systems.

Table 7-1 Comparison of FR4xx and F2xx Clock Systems
ParameterFR4xxF2xx
Maximum system frequency, fSYSTEM16 MHz or 24 MHz16 MHz
XT1 oscillatorSupports LF or LF and HF modes(1)Supports LF and HF modes
XT2 oscillatorNot availableSupports up to 16 MHz
DCO rangeFactory-provided frequencies only0.06 to 26 MHz
FLLAvailableNot available
REFOAvailable, low-power modeNot available
LFMODCLK (MODOSC/128)Not availableNot available
VLO controlAvailable with VLOAUTOOFFAvailable with OSCOFF in LPM4
Production calibrated frequenciesNone1 MHz, 8 MHz, 12 MHz, and 16 MHz
Clock sources for MCLKDCOCLKDIV, XT1CLK, REFOCLK, VLOCLKDCOCLK, VLOCLK, LFXT1CLK, or XT2CLK(2)
Clock sources for SMCLKMCLKDCOCLK, (LFXT1CLK and VLOCLK), or XT2CLK(2)
Clock sources for ACLKXT1CLK, REFOCLK, VLO(3)LFXT1CLK, VLOCLK(2)
External crystal fail-safe operationsXT1, LF: defaults to REFOCLK,
XT1, HF: defaults to DCOCLKDIV		For any crystal failure: OFIFG is set, MCLK sourced by crystal defaults to DCO.
Other clock sources do not have a fail‑safe option.
OFIE reset in fail-safe operationNot reset automaticallyReset automatically
RegistersCSCTL0 through CSCTL8DCOCTL, BCSCTL1 through BCSCTL3
DCO bits93
Internal load capacitors for XT1 oscillatorNot availableAvailable
(1) Some FR4xx MCUs support XT1 HF mode. See the device-specific data sheet for details.
(2) See the device-specific data sheet for the clock sources.
(3) Unlike in F2xx devices, VLOCLK cannot be selected as clock source of ACLK in most FR4xx devices. In the FR4xx family, the enhanced clock system devices including FR235x, FR215x, FR267x, and FR247x support VLO as the ACLK source. The VLO calibration method differs between F2xx and FR4xx devices (for details, see VLO calibration on the MSP430FR4xx and MSP430FR2xx family).

For more information about the clock system in the FR4xx devices, see the MSP430FR4xx and MSP430FR2xx family user's guide.