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  1.   Abstract
  2.   Trademarks
  3. 1Introduction: MSP Sigma-Delta ADCs and Common Applications
  4. 2MSP Sigma-Delta ADC Portfolio
  5. 3Sigma-Delta ADC Overview
  6. 4MSP Sigma-Delta ADC Features
    1. 4.1  ADC Inputs: Differential or Single-Ended
    2. 4.2  Input Channels: Independent or Multiplexed
    3. 4.3  Integrated Buffers
    4. 4.4  Integrated PGAs
    5. 4.5  Offset Calibration: Internal or External
    6. 4.6  Voltage Reference: Internal or External
    7. 4.7  ADC Modulator Clock Frequency: Fixed or Adjustable
    8. 4.8  Sampling Rate versus Data Rate
    9. 4.9  Conversion Mode: Single or Continuous
    10. 4.10 Groups of ADC Channels
    11. 4.11 Preload
    12. 4.12 Output Format: Unipolar or Bipolar Data
    13. 4.13 Module Synchronization
    14. 4.14 Architecture: Discrete-Time versus Continuous-Time
  7. 5Solutions to Common MSP Sigma-Delta ADC Configuration Issues
    1. 5.1 ADC Input Configuration
      1. 5.1.1 Settling Time Exceeds Recommended Minimum
      2. 5.1.2 Amplitude of the Input Signal Exceeds FSR
      3. 5.1.3 Missing Anti-Aliasing Filters
    2. 5.2 ADC Clocking Configuration
      1. 5.2.1 Incorrect Sampling Frequency
    3. 5.3 ADC Results
      1. 5.3.1 Unexpected Output Data Format
      2. 5.3.2 Low Resolution
      3. 5.3.3 Data Interpretation
    4. 5.4 Reference Module (REF) Configuration
      1. 5.4.1 Choosing Between an Internal or External Reference
      2. 5.4.2 Connecting the Recommended Capacitors
      3. 5.4.3 Delaying Conversions Until the Reference Settles
    5. 5.5 Hardware Recommendations
  8. 6Frequently Asked Questions
  9. 7References

6 Frequently Asked Questions

How do I calculate the effective number of bits (ENOB)?

For AC inputs, the ENOB can be calculated using Equation 5 and the SINAD values provided in the device-specific data sheet. For DC inputs, the ENOB equivalent is called the effective resolution and is not provided in the data sheet. The effective resolution can be calculated using the standard deviation from several samples of a known DC input. Other important performance parameters for DC inputs include integral nonlinearity (INL) and differential nonlinearity (DNL). For more details about the effective resolution, see the A bone of contention: ENOB or effective resolution? blog.

Equation 5. GUID-20200928-CA0I-LB1Z-ZKJB-CDMJ32VF0RGK-low.gif

Why can't I find the Sigma-Delta ADC sampling frequency in the data sheet?

The sampling frequency is typically not provided because it depends on the modulator frequency and the OSR. For some SD ADC modules, the modulator frequency and OSR are adjustable, so a pair of modulator frequency and OSR combinations can result in the same sampling frequency with different performance.

Can I use the differential ADC inputs as a single-ended ADC input?

Yes, but remember that this configuration halves the dynamic range. To learn more about dynamic range, see A Glossary of Analog-to-Digital Specifications and Performance Characteristics.

What's the difference between common-mode and differential input voltages?

Common-mode means the same voltage is applied to both the positive and negative ADC pins. In this case, the differential voltage would be zero (ignoring any noise or offsets) because there's no voltage difference between the pins. Common-mode and differential inputs can be applied simultaneously. For example, a DC bias could be applied to both pins while an AC signal is applied between the pins. See the device-specific data sheet for the absolute maximum ratings.

What type of decimation filter is used?

The SD ADC modules in Table 2-1 except SDHS feature second-order modulators and third-order (SINC3) decimation filters (also referred to as comb filters due to the shape of their frequency response). The SDHS module features a third-order modulator and multi-stage CIC decimation filters. To learn more about decimation filters, see Digital Filter Types in Delta-Sigma ADCs and the device-specific user's guide.

What does the frequency response of the decimation filter in the user's guide tell me?

The frequency response in the device-specific user's guide illustrates the level of attenuation at various input frequencies. Notches attenuate the input signal completely and occur at multiples of the sampling frequency (data rate). Typically, the minimum sampling frequency is based on the Nyquist rate, but a higher sampling frequency can be used to shift the first notch and reduce the roll-off attenuation of the input signal. Increasing the sampling frequency may reduce performance due to a lower OSR and will capture more harmonic content which may be desirable or not depending on the application. To learn more about roll-off attenuation, read the Quantifying harmonic distortion - Effect of sinc3 filter roll off blog.

If you decide to use a discrete ADC in your design, remember that some ADCs feature decimation filters with notches at 50 or 60 Hz to intentionally filter out noise from power supplies sourced by AC mains, so those ADCs should not be used in metering applications to measure AC power or energy.

Can I use external modulators with the internal decimation filters?

Yes, the SD24_B module supports external modulators. To learn more about this configuration, see the Multi-phase Energy Measurement with Isolated Shunt Sensors Reference Design (TIDA-00601).