SLAA998 May 2021 DAC43701 , DAC43701-Q1 , DAC53701 , DAC53701-Q1

Error Calculation and Thermal Management

The last term in the equation comes from the error in V_REF . It is important to note that all the terms involved in the calculation must have the same units. While gain error and offset error are specified in %FSR (full scale error), INL is specified in LSB. With these units, the following equation is represented as:

{E r r o r}_{C O D E} = V_{R E F} \times \frac{G a i n_E r r o r (% F S R)}{100} \times \frac{(C O D E - O f f s e t_C o d e)}{F u l l_C o d e} + V_{R E F} \times \frac{O f f s e t_E r r o r (% F S R)}{100} + R e a l_G a i n \times I N L + \frac{(V_{R E F} - V_{R E F_I D E A L})}{2^{D A C_r e s o l u t i o n}} \times C O D E

The real gain is found from the Gain_Error based on the following formula:

R e a l_G a i n = V_{R E F} \times (\frac{G a i n_E r r o r (% F S R)}{100} \times \frac{1}{F u l l_C o d e} + \frac{1}{2^{D A C_r e s o l u t i o n}})

For DAC53701, which is a 10-bit DAC, the full-code is 1023d and offset error is measured at 8d while for DAC43701, the full-code is 255d and the offset error is measured at 2d. In the external reference, the error in V_REF emerges from the error in VDD while in the internal reference the error in V_REF emerges from the internal reference of the DAC which is trimmed to have a value of 1.212V at room temperature (25°C). The trim resolution of this internal reference is around 5mV, so there can be an error of ±2.5mV.

Based on the gain setting in the internal mode, V_REF is given by:

V_{R E F} = {D A C}_{i n t e r n a l_r e f e r e n c e} \times G A I N

Gain settings of 1.5×, 2×, 3×, and 4× are provided and thus the error in V_REF is given by:

∆ V_{R E F} = ∆ {D A C}_{i n t e r n a l_r e f e r e n c e} \times G A I N

Similarly, these errors also drift with temperature and based on the gain error drift (%FSR/°C), offset error drift (%FSR/°C) and the drift in reference (ppm/°C) across temperature, one can find out the gain error, offset error and V_REF at a higher (or lower) temperature and use them in the previous equations to calculate the error at a different temperature.

{G a i n_E r r o r}_{T_{2}} (% F S R) = {G a i n_E r r o r}_{T_{1}} (% F S R) + G a i n_E r r o r_D r i f t (\frac{% F S R}{C}) \times (T_{2} - T_{1})

{O f f s e t_E r r o r}_{T_{2}} (% F S R) = {O f f s e t_E r r o r}_{T_{1}} (% F S R) + O f f s e t_E r r o r_D r i f t (\frac{% F S R}{C}) \times (T_{2} - T_{1})

The drift in the internal reference of the DAC is specified in ppm/°C (parts per million per deg. C) and its maximum value is 65 ppm/°C. Thus, the V_REF at a higher (or lower) temperature is given by the following equation:

V_{R E F_T 2} = V_{R E F_T_{a m b i e n t}} \times \frac{{D A C}_{i n t e r n a l_r e f e r e n c e_d r i f t} (\frac{p p m}{C})}{1 e 6} \times (T_{2} - T_{1}) + V_{R E F_T 1}

The ambient temperature is 25°C. To calculate the worst-case errors in second equation, take the maximum or minimum values of all the parameters involved to estimate the maximum or minimum error, respectively. The following table shows the minimum and maximum values of gain error, offset error, gain error drift and offset error drift for the internal mode of reference with a gain of 1.5×. The INL drift across temperature can be considered negligible in comparison to the other terms.

Offset error drift (MIN) (%FSR/C)	–2.23E-04	Gain error drift (MIN) (%FSR/C)	–1.50E-04
Offset error drift (MAX) (%FSR/C)	2.99E-04	Gain error drift (MAX) (%FSR/C)	–6.77E-05
Offset Error Min (%FSR)	–0.2571	Gain Error Min (%FSR)	–0.133
Offset Error Max (%FSR)	0.2698	Gain Error Max (%FSR)	0.09735

Also V_REF maximum can be estimated as the ideal V_REF of the following equation:

1.212 V \times 1.5 V = 1.818 V + 0.0025 V (e r r o r i n t h e i n t e r n a l r e f e r e n c e o f D A C) \times 1.5 V (g a i n s e t t i n g)

Similarly, V_REF minimum can be derived by 1.818V – 0.0025V × 1.5 = 1.81425V. Putting these maximum and minimum values and considering the maximum and minimum INL as +1 and –1 LSB respectively, using the second equation yields:

ERROR_{CODE_MAX} = 0.009719784V and V_{SET_MAX} = 1.009264706V

ERROR_{CODE_MIN} = –0.009804654V and V_{SET_MIN} = 0.989740268V

Similarly, by taking the drift values from the previous table and by considering a V_RFE drift of ±65ppm/°C, the following maximum and minimum errors are obtained (T1 = Tambient = 25°C) Error_{CODE_MAX_WITH_DRIFT} = 0.016760781V

ERROR_{CODE_MIN_WITH_DRIFT}= –0.01678633V

It is important to note that these errors have been calculated by adding all the maximum (or minimum) values of different errors in the same direction. In reality, this may not always be the case and some errors may diminish the effect of each other. Thus, the previous calculated errors are more pessimistic.

The feedback impedance (looking in impedance at the V_FB node) as well the load resistor tolerance of R_SET also has an impact on I_SET. The total impedance (R_tot) at the DAC feedback node will thus be a parallel combination of R_SET and R_VFB given by following equation:

R_{t o t} = \frac{{(R}_{S E T} \times R_{V F B})}{{(R}_{S E T} + R_{V F B})}

While R_SET has a tolerance of its own, R_VFB also varies from 160kΩ to 240kΩ for the internal reference gain of 1.5×. If we have an R_SET with 5% tolerance, the worst-case maximum and minimum values of R_tot will be:

R_{TOT_MAX} = 52.4885Ω

R_{TOT_MIN} = 47.4859Ω

With the V_{SET_MAX}, V_{SET_MIN}, R_{TOT_MAX}, R_{TOT_MIN} values, we can calculate the worst-case LED currents as follows:

I_{L E D_M A X} = \frac{V_{S E T_M A X}}{R_{T O T_M I N}}

I_{L E D_M I N} = \frac{V_{S E T_M I N}}{R_{T O T_M A X}}

From the previous two equations we get the worst-case I_{LED_MIN} and I_{LED_MAX} as 18.8563mA and 21.254mA, respectively. The total power dissipated across the MOSFET is given by:

P_{d i s} = {(V}_{D_M O S} - V_{S E T}) \times I_{S E T} = {(V}_{D_M O S} - V_{S E T}) \times (\frac{V_{S E T}}{R_{T O T}})

Where V_{D_MOS} is the drain voltage of the MOSFET. In this application, V_{D_MOS} will be VCC – VF where V_F is the voltage drop across the diodes. V_F depends on the I_SET flowing through them. The relationship between P_dis and V_SET is evident in the following figure showing MOSFET power dissipation and voltage set value.

If the V_SET for LED bright current condition is chosen to be greater than V_{D_MOS/2}, the power dissipation will be more when the LED dims down, that is, when the appliance door is closed. This is not a desirable condition so it is better to have V_SET below V_{D_MOS/2}, that is, (VCC – VF)/2.

It is also important to note that V_CC cannot be significantly reduced to reduce the power dissipation as there is also a V_F drop across the diodes to account for, and based on variation across I_SET, there should be a sufficient margin to cater to changes in V_F. In addition, reducing the V_CC reduces the V_DS of the MOSFET, and a drastic decrease in V_DS demands a higher V_GS to support the same I_SET which may cause certain headroom issues as mentioned in the previous sections.

The CSD16342Q5A MOSFET chosen for this example has a maximum junction-to-ambient thermal resistance, R_θJA of 50W/°C. With V_SET of 1V, V_CC of 5V and a typical V_F of 2V (single LED in the chain), P_DIS =

(5 - 2 - 1) \times 0.02 = 40 m W

This would mean a rise of $(0.04 \times 50) = 2^{o} C$ above the ambient temperature which is not much. However, care needs to be taken while dealing with higher currents.

For instance, a bright current of 200mA would give a P_DIS of 400mW implying a rise of 200°C above the ambient temperature. If the ambient temperature is close to the maximum operating temperature of the MOSFET, a 200°C rise may damage it.