SLAAE28A November 2021 – March 2022 DAC43204 , DAC53004 , DAC53204 , DAC53204W , DAC63004 , DAC63204
Register Address | Register Name | Setting | Description |
---|---|---|---|
0x01 | DAC-0-MARGIN-HIGH | 0x8000 | [15:4] 0x800: 10-bit data left adjusted updates the MARGIN-HIGH code |
[3:0] 0x0: Don't care | |||
0x02 | DAC-0-MARGIN-LOW | 0x0000 | [15:4] 0x000: 10-bit data left adjusted updates the MARGIN-LOW code |
[3:0] 0x0: Don't care | |||
0x06 | DAC-0-FUNC-CONFIG | 0x0001 | [15] 0b0: Write 0b1 to set DAC-0 clear setting to mid-scale |
[14] 0b0: Write 0b1 to update DAC-0 with LDAC trigger | |||
[13] 0b0: Write 0b1 to enable DAC-0 to be updated with broadcast command | |||
[12:11] 0b00: Selects phase for function generator | |||
[10:8] 0b000: Selects waveform generated by the function generator | |||
[7] 0b0: Write 0b1 to enable logarithmic slew | |||
[6:4] 0b000: Selects code-step of 1 LSB | |||
[3:0] 0b001: Selects slew-rate of 4 µs/step | |||
0x1F | COMMON-CONFIG | 0x0FF9 | [15] 0b0: Write 0b1 to set window-comparator output to a latching output |
[14] 0b0: Write 0b1 to lock device. Unlock by writing 0b0101 to DEV-UNLOCK field in the COMMON-TRIGGER register | |||
[13] 0b0: Write 0b1 to set fault-dump read enable at address 0x01 | |||
[12] 0b0: Write 0b1 to enables the internal reference | |||
[11:10] 0b11: Powers-down VOUT3 | |||
[9] 0b1: Powers-down IOUT3 | |||
[8:7] 0b11: Powers-down VOUT2 | |||
[6] 0b1: Powers-down IOUT2 | |||
[5:4] 0b11: Powers-down VOUT1 | |||
[3] 0b1: Powers-down IOUT1 | |||
[2:1] 0b00: Powers-up VOUT0 | |||
[0] 0b1: Powers-down IOUT0 | |||
0x20 | COMMON-TRIGGER | 0x0002 | [15:12] 0b0000: Write 0b0101 to unlock the device |
[11:8] 0b0000: Write 0b1010 to trigger a POR reset | |||
[7] 0b0: Write 0b1 to trigger LDAC operation if the respective SYNC-CONFIG-X bit in the DAC-X-FUNC-CONFIG register is 1 | |||
[6] 0b0: Write 0b1 to set the DAC registers and outputs to zero-code or mid-code based on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG register | |||
[5] 0b0: Don't care | |||
[4] 0b0: Write 0b1 to trigger fault-dump sequence | |||
[3] 0b0: Write 0b1 to trigger PROTECT function | |||
[2] 0b0: Write 0b1 to read one row of NVM for fault-dump | |||
[1] 0b1: Write 0b1 to store applicable register settings to the NVM | |||
[0] 0b0: Write 0b1 to reload applicable registers with existing NVM settings | |||
0x24 | GPIO-CONFIG | 0x4001 | [15] 0b0: Write 0b1 to enable glitch filter on GPI |
[14] 0b1: Enables deep-sleep function | |||
[13] 0b0: Write 0b1 to enable output mode on GPIO pin | |||
[12:9] 0b0000: STATUS function setting mapped to GPIO as output | |||
[8:5] 0b0000: Determines channels affected by channel-specific GPI functions | |||
[4:1] 0b0000: Selects GPI to trigger deep-sleep mode | |||
[0] 0b1: Enables input mode for GPIO pin |
Register Address | Register Name | Setting | Description |
---|---|---|---|
0x01 | DAC-0-MARGIN-HIGH | 0xFF00 | [15:4] 0xFF0: 8-bit data left adjusted updates the MARGIN-HIGH code |
[3:0] 0x0: Don't care | |||
0x02 | DAC-0-MARGIN-LOW | 0x8000 | [15:4] 0x800: 8-bit data left adjusted updates the MARGIN-LOW code |
[3:0] 0x0: Don't care | |||
0x06 | DAC-0-FUNC-CONFIG | 0x0001 | [15] 0b0: Write 0b1 to set DAC-0 clear setting to mid-scale |
[14] 0b0: Write 0b1 to update DAC-0 with LDAC trigger | |||
[13] 0b0: Write 0b1 to enable DAC-0 to be updated with broadcast command | |||
[12:11] 0b00: Selects phase for function generator | |||
[10:8] 0b000: Selects waveform generated by the function generator | |||
[7] 0b0: Write 0b1 to enable logarithmic slew | |||
[6:4] 0b000: Selects code-step of 1 LSB | |||
[3:0] 0b001: Selects slew-rate of 4 µs/step | |||
0x1F | COMMON-CONFIG | 0x0FFE | [15] 0b0: Write 0b1 to set window-comparator output to a latching output |
[14] 0b0: Write 0b1 to lock device. Unlock by writing 0b0101 to DEV-UNLOCK field in the COMMON-TRIGGER register | |||
[13] 0b0: Write 0b1 to set fault-dump read enable at address 0x01 | |||
[12] 0b0: Write 0b1 to enables the internal reference | |||
[11:10] 0b11: Powers-down VOUT3 | |||
[9] 0b1: Powers-down IOUT3 | |||
[8:7] 0b11: Powers-down VOUT2 | |||
[6] 0b1: Powers-down IOUT2 | |||
[5:4] 0b11: Powers-down VOUT1 | |||
[3] 0b1: Powers-down IOUT1 | |||
[2:1] 0b11: Powers-down VOUT0 | |||
[0] 0b0: Powers-up IOUT0 | |||
0x20 | COMMON-TRIGGER | 0x0002 | [15:12] 0b0000: Write 0b0101 to unlock the device |
[11:8] 0b0000: Write 0b1010 to trigger a POR reset | |||
[7] 0b0: Write 0b1 to trigger LDAC operation if the respective SYNC-CONFIG-X bit in the DAC-X-FUNC-CONFIG register is 1 | |||
[6] 0b0: Write 0b1 to set the DAC registers and outputs to zero-code or mid-code based on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG register | |||
[5] 0b0: Don't care | |||
[4] 0b0: Write 0b1 to trigger fault-dump sequence | |||
[3] 0b0: Write 0b1 to trigger PROTECT function | |||
[2] 0b0: Write 0b1 to read one row of NVM for fault-dump | |||
[1] 0b1: Write 0b1 to store applicable register settings to the NVM | |||
[0] 0b0: Write 0b1 to reload applicable registers with existing NVM settings | |||
0x24 | GPIO-CONFIG | 0x4001 | [15] 0b0: Write 0b1 to enable glitch filter on GPI |
[14] 0b1: Enables deep-sleep function | |||
[13] 0b0: Write 0b1 to enable output mode on GPIO pin | |||
[12:9] 0b0000: STATUS function setting mapped to GPIO as output | |||
[8:5] 0b0000: Determines channels affected by channel-specific GPI functions | |||
[4:1] 0b0000: Selects GPI to trigger deep-sleep mode | |||
[0] 0b1: Enables input mode for GPIO pin |