SLAAE33 September 2021 DAC43204 , DAC43401 , DAC43701 , DAC43701-Q1 , DAC53204 , DAC53401 , DAC53701 , DAC53701-Q1 , LM555 , LMC555 , NA555 , NE555 , SA555 , SE555 , TLC555

3 Pulse Generator with Variable Frequency and Variable Duty Cycle

The designer can use the 555 timer in a stable operation to create an output pulse train with variable frequency and variable duty cycle. If 50% duty cycle is required, the simpler configuration shown in Figure 3-1 can be used. If a duty cycle other than 50% is required, the configuration shown in Figure 3-3 can be used.

Figure 3-1 555 Timer Configured for a 50% Duty Cycle Oscillator

In the 50% duty cycle configuration, the circuit is configured with the TRIG and THRESH pins tied together, which causes the circuit to re-trigger after every timing cycle. During each cycle, the capacitor charges up to the upper comparator limit of ⅔ × VDD through the external R and C and then discharges down to the lower comparator limit of ⅓ × VDD through the same external R and C. Using Equation 1 for the capacitor voltage (V_CAP) in an RC circuit, it is shown that the time to charge from ⅓ × VDD to ⅔ × VDD is equal to Equation 3:

Equation 1.

V_{C A P} (t) = V (1 - e^{- t / R C})

Equation 2.

t = - R C \times l n (1 - \frac{V_{C} (t)}{V})

If V = VDD, V_CAP(t₁) = ⅓ × VDD, and V_CAP (t₂) = ⅔ × VDD, Equation 2 can be rewritten as:

Equation 3.

t_{c h a r g e} = t_{2} - t_{1} = - R C \times l n (\frac{1}{3}) + RC \times \ln (\frac{2}{3}) = 0.693 \times R C

Because the discharge time from ⅔ × VDD to ⅓ × VDD uses the same external R and C, the discharge time is equal to Equation 3:

Equation 4.

t_{d i s c h a r g e} = 0.693 \times R C

The equal charge and discharge times produce a 50% duty cycle waveform with the frequency defined in Equation 5:

Equation 5.

f = \frac{1}{t_{c h a r g e} + t_{d i s c h a r g e}} = \frac{1}{1.386 \times R C}

During a charging event, the OUT pin retains a high state and during a discharge event the OUT pin holds a low state. The 50% duty cycle configuration relies on OUT having a high voltage output (VOH) and low voltage output (VOL) be driven symmetrically with respect to the supply rails for tcharge to equal tdischarge. This symmetry is a characteristic of CMOS 555 timers. A bipolar 555 timer does not have symmetrical VOH/VOL characteristics and would not yield a 50% duty cycle in this configuration.

Figure 3-2 shows the resulting waveforms for a 1.5-kHz waveform with 50% duty cycle. Note that the DISCH pin can be used as an alternate output with drive characteristics on the discharge path and an external pull-up resistor.

VS = 5 V, R = 1 kΩ, C = 470 nF

Figure 3-2 TINA-TI Simulation Results for a 50% Duty Cycle Oscillator Using a 555 Timer

In the variable duty cycle configuration shown in Figure 3-3 the circuit is also configured with the TRIG and THRESH pins tied together, but the resistor and capacitor configuration is changed such that the capacitor charges through both R_A and R_B and the capacitor discharges through only R_B.

Figure 3-3 555 Timer Configured for a Variable Duty Cycle Oscillator

This creates the asymmetric charge and discharge timings of Equation 6 and Equation 7. During a charge event, the OUT pin holds a high state and during a discharge event the OUT pin holds a low state. The configurable charge and discharge times produce a variable duty cycle waveform with the frequency defined in Equation 8 and a duty cycle defined in Equation 9.

Equation 6.

t_{c h a r g e} = 0.693 \times (R_{A} + R_{B}) \times C

Equation 7.

t_{d i s c h a r g e} = 0.693 \times R_{B} C

Equation 8.

f = \frac{1}{t_{c h a r g e} + t_{d i s c h a r g e}} = \frac{1}{0.693 \times (R_{A} + 2 R_{B}) \times C}

Equation 9.

D u t y C y c l e = \frac{t_{c h a r g e}}{t_{c h a r g e} + t_{d i s c h a r g e}} = \frac{R_{A} + R_{B}}{R_{A} + 2 R_{B}}

Figure 3-4 shows the resulting waveforms for a 1.5-kHz output with a 62.5% duty cycle.

VS = 5 V, R_A = 5 kΩ, R_B = 7.5 kΩ C = 47 nF

Figure 3-4 TINA-TI Simulation Results for a Variable Duty Cycle Oscillator Configuration Using a 555 Timer

Alternatively, the designer can use a smart DAC such as the DAC53701 to create an output pulse train with variable frequency and variable duty cycle. The CWG mode of the DAC53701 has the ability to output triangle waves, sawtooth waves with rising or falling slopes, and square waves. Configuration registers are available to customize the slew rate and the high and low voltage levels of the output. This circuit is shown in Figure 3-5.

The function generator can create a 50% duty-cycle square wave with a limited number of adjustable frequencies. The frequency is given in Equation 10:

Equation 10.

f = \frac{1}{2 \times S L E W_R A T E}

Where: SLEW_RATE is the time per high and low pulse of the square waveform.

A 50% duty cycle output pulse train with a greater number of frequencies, or a pulse train with duty cycles other than 50% can be created by using the DAC53701 in CWG mode and applying a fixed input voltage on the feedback pin (VFB) of the DAC. The DAC53701 can create a triangle wave with a frequency given by:

Equation 11.

f = \frac{1}{2 \times S L E W_R A T E \times (\frac{M A R G I N_H I G H - M A R G I N_L O W + 1}{C O D E_S T E P})}

Where:

SLEW_RATE is given in time per step.

MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.

CODE_STEP is the programmable number of DAC codes per step.

The margin-high voltage is the high-voltage level of the waveform, and the margin-low voltage is the low-voltage level. The pulse train frequency will be equal to the frequency of the triangle wave generated by the DAC. The duty cycle of the pulse train output correlates with the margin-high voltage, margin-low voltage and voltage applied to the feedback pin (VFB), as expressed by:

Equation 12.

D u t y C y c l e = \frac{M A R G I N_H I G H_V O L T A G E - V F B}{M A R G I N_H I G H_V O L T A G E - M A R G I N_L O W_V O L T A G E}

Figure 3-5 DAC53701 Configured for a Variable Duty Cycle Oscillator

Figure 3-6 shows the resulting waveforms for a 1.5-kHz output with a 60% duty cycle. An NMOS transistor may be added to the output of the DAC53701 to sharpen the edges of the output, but note this will inverse the duty cycle as shown in the simulation.

VS = 5 V, MARGIN_HIGH_CODE = 810, MARGIN_LOW_CODE = 310, CODE_STEP = 32, SLEW_RATE = 4 µs/step, MARGIN_HIGH = 4 V, MARGIN_LOW = 1.5 V, VDAC = 1.5-kHz triangle wave, and VFB = 2.5 V

Figure 3-6 TINA-TI Simulation Results for a Variable Duty Cycle Oscillator Using a DAC53701

The 555 timer relies on an external capacitor as its core timing element and these components often have large tolerances on the order of 20%, leading to large variation in the output frequency. The smart DAC presents a superior option due to the internal oscillator having an accuracy of 5%.