Design Notes

The DACx3204 12-Bit, 10-Bit, and 8-Bit, Quad Voltage and Current Output Smart DACs With Auto-Detected I2C, PMBus™, or SPI data sheet recommends using a 100-nF decoupling capacitor for the VDD pin and a 1.5-µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal low-dropout regulator (LDO). Place these capacitors close to the device pins.
When the external reference is not used, the data sheet recommends the VREF pin be connected to VDD through a pullup resistor.
The example circuit shows two methods for controlling the LED current. Current can be set via a R_SET resistor and varying the base voltage of an external PNP-type BJT with the DACx3204 output, or the LED current can be set using the current output mode of the DACx3204.
1. To adjust the current LED current with the external BJT, select an R_SET resistor and vary the base voltage with the DAC output. R_SET is calculated by:
  $R_{S E T} = \frac{V_{S E T}}{I_{L E D}}$
  If the V_SET voltage range is chosen to be 0 V to 1 V, and the required LED current range is 0 mA to 20 mA, R_SET is calculated to be:
  $R_{S E T} = \frac{1 V}{20 m A} = 50 Ω$
  The DAC codes for the 10-bit DAC53204 can be calculated by:
  $C o d e = \frac{V_{D A C}}{V_{R E F}} \times 1024$
  V_DAC is calculated by:
  $V_{D A C} = V D D - V_{S E T}$
  If a 5-V VDD is used as the reference, the high and low DAC codes become:
  $C o d e = \frac{5 V - 0}{5 V} \times 1024 = 1024 d$
  $C o d e = \frac{5 V - 1 V}{5 V} \times 1024 = 819.2 d$
  This is rounded to 1023d and 819d to give a high value of 4.995 V and low value of 3.999 V. This configuration compensates the V_BE voltage drop caused by temperature, collector current, and aging of the BJT. A BJT provides a smaller V_BE drop as compared to a typical gate-source voltage (V_GS) drop of a MOSFET.
2. The DAC can be used in current output mode to drive the LED directly with up to 250 µA. With the ±250 µA range selected, the DAC codes are calculated by:
  $C o d e = \frac{(I_{D A C} - I_{M I N}) \times 256}{I_{M A X} - I_{M I N}}$
  The high and low DAC53204 codes become:
  $C o d e = \frac{(0 µ A + 250 µ A) \times 256}{250 µ A + 250 µ A} = 128 d$
  $C o d e = \frac{(- 250 µ A + 250 µ A) \times 256}{250 µ A + 250 µ A} = 0 d$
The slew rate between the high and low DAC codes can be programmed if these two values are stored in the MARGIN-HIGH and MARGIN-LOW DAC registers. The slew time is determined by the settings in the SLEW-RATE and CODE-STEP fields in the DAC-X-FUNC-CONFIG register. The slew time is given by:
$S l e w T i m e = \frac{(M A R G I N_H I G H_C O D E - M A R G I N_L O W_C O D E + 1)}{C O D E_S T E P} \times S L E W_R A T E$
If the CODE-STEP is set to 1 LSB, and the SLEW-RATE is set to 4 µs per step, the slew time for the voltage configuration becomes:
$S l e w T i m e = \frac{(1023 - 819 + 1)}{1} \times 4 µ s = 0.82 m s$
The slew time for the current output configuration becomes:
$S l e w T i m e = \frac{(128 - 0 + 1)}{1} \times 4 µ s = 0.516 m s$
The GPIO pin of the DACx3204 can be used to toggle between the margin high and margin low output value based on the slew time settings set in the DAC-X-FUNC-CONFIG register. A high on the GPI triggers the output to slew to the margin high value. A low on the GPI triggers the output to slew to the margin low value. The register settings to enable the GPIO for this function are described in the Register Settings section.
The DACx3204 can be programmed with the initial register settings described in the Register Settings section using I²C or SPI. The initial register settings can be saved in the NVM by writing a 1 to the NVM-PROG field of the COMMON-TRIGGER register. After programming the NVM, the device loads all registers with the values stored in the NVM after a reset or a power cycle.