SLAAE64 may   2023 AFE58JD48 , DAC81001 , DAC8801 , DAC8830 , OPA2210 , REF5010 , REF5040 , THS4130

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Proposed Topologies
    1. 2.1 Proposal 1: Using R-2R DAC (DAC8830)
      1. 2.1.1 Highlighted Products
        1. 2.1.1.1 DAC8830
        2. 2.1.1.2 OPA2210
        3. 2.1.1.3 THS4130
        4. 2.1.1.4 REF5040
      2. 2.1.2 Design Circuit
      3. 2.1.3 PSpice-TI Simulation
    2. 2.2 Proposal 2: Using M-DAC (DAC8801)
      1. 2.2.1 Highlighted Products
        1. 2.2.1.1 DAC8801
        2. 2.2.1.2 OPA2210
        3. 2.2.1.3 THS4130
        4. 2.2.1.4 REF5010
      2. 2.2.2 Design Circuit
      3. 2.2.3 PSpice-TI Simulation
    3. 2.3 Proposal 3: Using Low-Noise R-2R DAC (DAC81001)
      1. 2.3.1 Highlighted Products
        1. 2.3.1.1 DAC81001
        2. 2.3.1.2 OPA2210
        3. 2.3.1.3 THS4130
        4. 2.3.1.4 REF5010
      2. 2.3.2 Design Circuit
      3. 2.3.3 PSpice-TI Simulation
  6. 3Conclusion
  7. 4References

2.3.2 Design Circuit

This method uses a low-noise R-2R-DAC for the TGC control circuit. Figure 2-12 shows a high-level block diagram for the topology. There are two reference voltages for the DAC, VREF+ = 10 V, VREF– = –10 V. The DAC81001 outputs are unbuffered, in such scenario, a low-noise external buffer must be used. Figure 2-13 shows the drive circuit for the control voltage.


GUID-20221116-SS0I-MD8Z-8SBK-PJL37DHFPM3T-low.svg

Figure 2-12 A Low-Noise R-2R DAC Used in Generating a TGC Signal

GUID-20221116-SS0I-Q4SQ-CMT9-MPZ5D960G5CJ-low.svg

Figure 2-13 Proposal 3-VCNTL Drive Circuit