SLAAE64 may   2023 AFE58JD48 , DAC81001 , DAC8801 , DAC8830 , OPA2210 , REF5010 , REF5040 , THS4130

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Proposed Topologies
    1. 2.1 Proposal 1: Using R-2R DAC (DAC8830)
      1. 2.1.1 Highlighted Products
        1. 2.1.1.1 DAC8830
        2. 2.1.1.2 OPA2210
        3. 2.1.1.3 THS4130
        4. 2.1.1.4 REF5040
      2. 2.1.2 Design Circuit
      3. 2.1.3 PSpice-TI Simulation
    2. 2.2 Proposal 2: Using M-DAC (DAC8801)
      1. 2.2.1 Highlighted Products
        1. 2.2.1.1 DAC8801
        2. 2.2.1.2 OPA2210
        3. 2.2.1.3 THS4130
        4. 2.2.1.4 REF5010
      2. 2.2.2 Design Circuit
      3. 2.2.3 PSpice-TI Simulation
    3. 2.3 Proposal 3: Using Low-Noise R-2R DAC (DAC81001)
      1. 2.3.1 Highlighted Products
        1. 2.3.1.1 DAC81001
        2. 2.3.1.2 OPA2210
        3. 2.3.1.3 THS4130
        4. 2.3.1.4 REF5010
      2. 2.3.2 Design Circuit
      3. 2.3.3 PSpice-TI Simulation
  6. 3Conclusion
  7. 4References

2.1.2 Design Circuit

Figure 2-1 shows a high-level block diagram for the topology using a R-2R-DAC to generate the drive for VCNTL. This method uses the REF5040 as the reference voltage source and the VOCM (1.3 V) is obtained by the resistor divider, the output voltage has a typical requirement of low noise and fast settling.


GUID-20221116-SS0I-SHTC-90HG-C1LLV14SR0CJ-low.svg

Figure 2-1 A R-2R DAC Used in Generating a TGC Signal

The output of the DAC is buffered first and then followed by attenuation, helps attenuate noise contributions from the reference circuit and the DAC. Figure 2-2 shows the entire drive circuit for the control voltage.


GUID-20221116-SS0I-PWT3-5KTF-QQX3LXVGWSNJ-low.svg

Figure 2-2 Proposal 1-VCNTL Drive Circuit