SLAAE76B march   2023  – june 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0G Hardware Design Check List
  5. 2 Power Supplies in MSPM0G Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug port pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    6. 8.6 Communicate With a 1.8-V Device Without a Level Shifter
    7. 8.7 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11References
  15. 12Revision History

1 MSPM0G Hardware Design Check List

Table 1-1 describes the main contents that needs to be checked during the MSPM0G hardware design process. The following sections provide more details.

Table 1-1 MSPM0G Hardware Design Check List
Pin Description Requirements
VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins.
VSS Power supply negative pin
VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin.
NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.
ROSC External reference resistor pin
  • Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed.
  • Can be left open the application does not have high accuracy requirement for SYSOSC.
VREF+ Voltage reference power supply - external reference input
  • When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source.
  • Leaving open is OK if the application does not need external voltage reference.
VREF- Voltage reference ground supply - external reference input
SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part.
SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part.
PA0, PA1 Open-drain I/O Pullup resistor required for output high
PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.)
PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor.
Note: For any unused pin with a function that is shared with general-purpose I/O, follow the "PAx" unused pin connection guidelines.

TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters).

The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.

The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor is not required if the SYSOSC FCL is not enabled.

For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals.

A 0.47-µF tank capacitor is required for the VCORE pin and need to be placed close to the device with minimum distance to the device ground.

For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for I2C and UART functions if the ODIO are used.

GUID-20211118-SS0I-GV3N-3FKW-FTQJHQ5V6VQK-low.svg Figure 1-1 MSPM0G Typical Application Schematic