SLAAE76B march 2023 – june 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507
8.5 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in Figure 8-1, TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see Top map MSPM0 G-Series MCUs Hardware Development Guide MSPM0 G-Series MCUs Hardware Development Guide Abstract Abstract Table of Contents Table of Contents Trademarks Trademarks MSPM0G Hardware Design Check List MSPM0G Hardware Design Check List Power Supplies in MSPM0G Devices Power Supplies in MSPM0G Devices Digital Power Supply Digital Power Supply Analog Power Supply Analog Power Supply Built-in Power Supply and Voltage Reference Built-in Power Supply and Voltage Reference Recommended Decoupling Circuit for Power Supply Recommended Decoupling Circuit for Power Supply Reset and Power Supply Supervisor Reset and Power Supply Supervisor Digital Power Supply Digital Power Supply Power Supply Supervisor Power Supply Supervisor Clock System Clock System Internal Oscillators Internal Oscillators External Oscillators External Oscillators External Clock Output (CLK_OUT) External Clock Output (CLK_OUT) Frequency Clock Counter (FCC) Frequency Clock Counter (FCC) Debugger Debugger Debug port pins and Pinout Debug port pins and Pinout Debug Port Connection With Standard JTAG Connector Debug Port Connection With Standard JTAG Connector Key Analog Peripherals Key Analog Peripherals ADC Design Considerations ADC Design Considerations OPA Design Considerations OPA Design Considerations DAC Design Considerations DAC Design Considerations COMP Design Considerations COMP Design Considerations GPAMP Design Considerations GPAMP Design Considerations Key Digital Peripherals Key Digital Peripherals Timer Resources and Design Considerations Timer Resources and Design Considerations UART and LIN Resources and Design Considerations UART and LIN Resources and Design Considerations MCAN Design Considerations MCAN Design Considerations I2C and SPI Design Considerations I2C and SPI Design Considerations GPIOs GPIOs GPIO Output Switching Speed and Load Capacitance GPIO Output Switching Speed and Load Capacitance GPIO Current Sink and Source GPIO Current Sink and Source High-Speed GPIOs (HSIO) High-Speed GPIOs (HSIO) High-Drive GPIOs (HDIO) High-Drive GPIOs (HDIO) Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter Communicate With a 1.8-V Device Without a Level Shifter Communicate With a 1.8-V Device Without a Level Shifter Unused Pins Connection Unused Pins Connection Layout Guides Layout Guides Power Supply Layout Power Supply Layout Considerations for Ground Layout Considerations for Ground Layout Traces, Vias, and Other PCB Components Traces, Vias, and Other PCB Components How to Select Board Layers and Recommended Stack-up How to Select Board Layers and Recommended Stack-up Bootloader Bootloader Bootloader Introduction Bootloader Introduction Bootloader Hardware Design Considerations Bootloader Hardware Design Considerations Physical Communication interfaces Physical Communication interfaces Hardware Invocation Hardware Invocation References References Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER MSPM0 G-Series MCUs Hardware Development Guide MSPM0 G-Series MCUs Hardware Development Guide Abstract The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance. Abstract The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance. The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance. The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance. The MSPM0 G-series microcontroller (MCU) portfolio offers a wide variety of 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement, and control applications. This application note covers information needed for hardware development with MSPM0 G series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance. Table of Contents yes 2 yes yes Table of Contents yes 2 yes yes yes 2 yes yes yes2yesyes Trademarks Trademarks MSPM0G Hardware Design Check List B 20230531 Updated the numbering format for tables, figures and cross-references throughout the document. yes B 20230531 Updated #GUID-1A977700-740B-4239-9646-73672C96D3CA. yes #GUID-1A977700-740B-4239-9646-73672C96D3CA/GUID-9D414E7A-A6E4-4DCE-A5B5-9492C6B1C56D describes the main contents that needs to be checked during the MSPM0G hardware design process. The following sections provide more details. MSPM0G Hardware Design Check List Pin Description Requirements VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. For any unused pin with a function that is shared with general-purpose I/O, follow the "PAx" unused pin connection guidelines. TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor is not required if the SYSOSC FCL is not enabled. For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals. A 0.47-µF tank capacitor is required for the VCORE pin and need to be placed close to the device with minimum distance to the device ground. For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for I2C and UART functions if the ODIO are used. MSPM0G Typical Application Schematic MSPM0G Hardware Design Check List B 20230531 Updated the numbering format for tables, figures and cross-references throughout the document. yes B 20230531 Updated #GUID-1A977700-740B-4239-9646-73672C96D3CA. yes B 20230531 Updated the numbering format for tables, figures and cross-references throughout the document. yes B 20230531 Updated #GUID-1A977700-740B-4239-9646-73672C96D3CA. yes B 20230531 Updated the numbering format for tables, figures and cross-references throughout the document. yes B20230531Updated the numbering format for tables, figures and cross-references throughout the document.yes B 20230531 Updated #GUID-1A977700-740B-4239-9646-73672C96D3CA. yes B20230531Updated #GUID-1A977700-740B-4239-9646-73672C96D3CA.#GUID-1A977700-740B-4239-9646-73672C96D3CAyes #GUID-1A977700-740B-4239-9646-73672C96D3CA/GUID-9D414E7A-A6E4-4DCE-A5B5-9492C6B1C56D describes the main contents that needs to be checked during the MSPM0G hardware design process. The following sections provide more details. MSPM0G Hardware Design Check List Pin Description Requirements VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. For any unused pin with a function that is shared with general-purpose I/O, follow the "PAx" unused pin connection guidelines. TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor is not required if the SYSOSC FCL is not enabled. For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals. A 0.47-µF tank capacitor is required for the VCORE pin and need to be placed close to the device with minimum distance to the device ground. For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for I2C and UART functions if the ODIO are used. MSPM0G Typical Application Schematic #GUID-1A977700-740B-4239-9646-73672C96D3CA/GUID-9D414E7A-A6E4-4DCE-A5B5-9492C6B1C56D describes the main contents that needs to be checked during the MSPM0G hardware design process. The following sections provide more details.#GUID-1A977700-740B-4239-9646-73672C96D3CA/GUID-9D414E7A-A6E4-4DCE-A5B5-9492C6B1C56D MSPM0G Hardware Design Check List Pin Description Requirements VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. MSPM0G Hardware Design Check List Pin Description Requirements VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. Pin Description Requirements Pin Description Requirements PinDescriptionRequirements VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. VDD Power supply positive pin Place 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VDDPower supply positive pinPlace 10-µF and 100-nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins. VSS Power supply negative pin VSSPower supply negative pin VCORE Core voltage (typical: 1.35V) Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. VCORECore voltage (typical: 1.35V)Connect a 470-nF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin. NRST Reset pin Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. NRSTReset pinConnect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. ROSC External reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. ROSCExternal reference resistor pin Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed. Can be left open the application does not have high accuracy requirement for SYSOSC. Connect an external 100-kΩ/±0.1%, 25-ppm resistor to VSS to enable high SYSOSC accuracy if needed.Can be left open the application does not have high accuracy requirement for SYSOSC. VREF+ Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. VREF+Voltage reference power supply - external reference input When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Leaving open is OK if the application does not need external voltage reference. When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source.Leaving open is OK if the application does not need external voltage reference. VREF- Voltage reference ground supply - external reference input VREF-Voltage reference ground supply - external reference input SWCLK Serial wire clock from debug probe Internal pulldown to VSS, does not need any external part. SWCLKSerial wire clock from debug probeInternal pulldown to VSS, does not need any external part. SWDIO Bidirectional (shared) serial wire data Internal pullup to VDD, does not need any external part. SWDIOBidirectional (shared) serial wire dataInternal pullup to VDD, does not need any external part. PA0, PA1 Open-drain I/O Pullup resistor required for output high PA0, PA1Open-drain I/OPullup resistor required for output high PA18 Default BSL invoke Pin Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PA18Default BSL invoke PinKeep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) PAx (exclude PA0, PA1) General-purpose I/O Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. PAx (exclude PA0, PA1)General-purpose I/OSet corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor.For any unused pin with a function that is shared with general-purpose I/O, follow the "PAx" unused pin connection guidelines.TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters).The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor is not required if the SYSOSC FCL is not enabled.For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals. A 0.47-µF tank capacitor is required for the VCORE pin and need to be placed close to the device with minimum distance to the device ground.For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for I2C and UART functions if the ODIO are used. MSPM0G Typical Application Schematic MSPM0G Typical Application Schematic Power Supplies in MSPM0G Devices Power is supplied to the device through the VDD and VSS connections. The device supports operation with a supply voltage of 1.62 V to 3.6 V and can start with a 1.62-V supply. The power management unit (PMU) generates the regulated core supplies for the device and provides supervision of the external supply. It also contains a bandgap voltage reference used by the PMU and other analog peripherals. VDD is used directly to provide the IO supply (VDDIO) and the analog supply (VDDA). VDDIO and VDDA are internally connected to VDD so that additional power supply pins are not required (see the device data sheet for details). Digital Power Supply VCORE Regulator An internal low-dropout linear voltage regulator generates a 1.35-V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. The core regulator requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground) (see ). See the device-specific data sheet for the correct value and tolerance of CVCORE. CVCORE should be placed close to the VCORE pin. The core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance. VCORE Regulator Circuit Analog Power Supply Analog Mux VBOOST The VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range. Enabling and Disabling VBOOST SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters: The COMP, OPA, and GPAMP peripheral PWREN settings The MODE setting of any COMP which is enabled (FAST vs. ULP mode). The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL. VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral. The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time. Bandgap Reference The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including: Driving the brownout reset circuit thresholds. Setting the output voltage for the core regulator. Driving the on-chip VREF levels for on-chip analog peripherals. The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required. Built-in Power Supply and Voltage Reference The VREF module for the MSPM0G family is a shared voltage reference module that can be leveraged by a variety on on-board analog peripherals. The VREF module features include: 1.4-V and 2.5-V user-selectable internal references. Support for receiving external reference on the VREF+ and VREF- device pins. Sample and hold mode support VREF operation down to STANDBY operating mode. Internal reference supports for ADC, COMP, and OPA. When supplying the MCU with an external reference, TI recommends connecting a decoupling capacitor on the reference pins with a value based on the voltage source (see ). VREF Circuit Recommended Decoupling Circuit for Power Supply TI recommends connecting a combination of a 10-μF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC pin (see ). Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Power Supply Decoupling Circuit Power Supplies in MSPM0G Devices Power is supplied to the device through the VDD and VSS connections. The device supports operation with a supply voltage of 1.62 V to 3.6 V and can start with a 1.62-V supply. The power management unit (PMU) generates the regulated core supplies for the device and provides supervision of the external supply. It also contains a bandgap voltage reference used by the PMU and other analog peripherals. VDD is used directly to provide the IO supply (VDDIO) and the analog supply (VDDA). VDDIO and VDDA are internally connected to VDD so that additional power supply pins are not required (see the device data sheet for details). Power is supplied to the device through the VDD and VSS connections. The device supports operation with a supply voltage of 1.62 V to 3.6 V and can start with a 1.62-V supply. The power management unit (PMU) generates the regulated core supplies for the device and provides supervision of the external supply. It also contains a bandgap voltage reference used by the PMU and other analog peripherals. VDD is used directly to provide the IO supply (VDDIO) and the analog supply (VDDA). VDDIO and VDDA are internally connected to VDD so that additional power supply pins are not required (see the device data sheet for details). Digital Power Supply VCORE Regulator An internal low-dropout linear voltage regulator generates a 1.35-V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. The core regulator requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground) (see ). See the device-specific data sheet for the correct value and tolerance of CVCORE. CVCORE should be placed close to the VCORE pin. The core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance. VCORE Regulator Circuit Digital Power Supply VCORE Regulator An internal low-dropout linear voltage regulator generates a 1.35-V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. The core regulator requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground) (see ). See the device-specific data sheet for the correct value and tolerance of CVCORE. CVCORE should be placed close to the VCORE pin. The core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance. VCORE Regulator Circuit VCORE Regulator VCORE Regulator VCORE Regulator An internal low-dropout linear voltage regulator generates a 1.35-V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. The core regulator requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground) (see ). See the device-specific data sheet for the correct value and tolerance of CVCORE. CVCORE should be placed close to the VCORE pin. The core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance. VCORE Regulator Circuit An internal low-dropout linear voltage regulator generates a 1.35-V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. The core regulator requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground) (see ). See the device-specific data sheet for the correct value and tolerance of CVCORE. CVCORE should be placed close to the VCORE pin.VCOREVCOREThe core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance. VCORE Regulator Circuit VCORE Regulator CircuitCORE Analog Power Supply Analog Mux VBOOST The VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range. Enabling and Disabling VBOOST SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters: The COMP, OPA, and GPAMP peripheral PWREN settings The MODE setting of any COMP which is enabled (FAST vs. ULP mode). The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL. VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral. The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time. Bandgap Reference The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including: Driving the brownout reset circuit thresholds. Setting the output voltage for the core regulator. Driving the on-chip VREF levels for on-chip analog peripherals. The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required. Analog Power Supply Analog Mux VBOOST The VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range. Enabling and Disabling VBOOST SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters: The COMP, OPA, and GPAMP peripheral PWREN settings The MODE setting of any COMP which is enabled (FAST vs. ULP mode). The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL. VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral. The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time. Bandgap Reference The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including: Driving the brownout reset circuit thresholds. Setting the output voltage for the core regulator. Driving the on-chip VREF levels for on-chip analog peripherals. The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required. Analog Mux VBOOST The VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range. Analog Mux VBOOSTThe VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range. Enabling and Disabling VBOOST Enabling and Disabling VBOOST SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters: The COMP, OPA, and GPAMP peripheral PWREN settings The MODE setting of any COMP which is enabled (FAST vs. ULP mode). The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL. VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral. The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time. SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters: The COMP, OPA, and GPAMP peripheral PWREN settings The MODE setting of any COMP which is enabled (FAST vs. ULP mode). The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL. The COMP, OPA, and GPAMP peripheral PWREN settingsThe MODE setting of any COMP which is enabled (FAST vs. ULP mode).The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL.VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral.The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time. Bandgap Reference Bandgap Reference The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including: Driving the brownout reset circuit thresholds. Setting the output voltage for the core regulator. Driving the on-chip VREF levels for on-chip analog peripherals. The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required. The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including: Driving the brownout reset circuit thresholds. Setting the output voltage for the core regulator. Driving the on-chip VREF levels for on-chip analog peripherals. Driving the brownout reset circuit thresholds.Setting the output voltage for the core regulator.Driving the on-chip VREF levels for on-chip analog peripherals.The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required. Built-in Power Supply and Voltage Reference The VREF module for the MSPM0G family is a shared voltage reference module that can be leveraged by a variety on on-board analog peripherals. The VREF module features include: 1.4-V and 2.5-V user-selectable internal references. Support for receiving external reference on the VREF+ and VREF- device pins. Sample and hold mode support VREF operation down to STANDBY operating mode. Internal reference supports for ADC, COMP, and OPA. When supplying the MCU with an external reference, TI recommends connecting a decoupling capacitor on the reference pins with a value based on the voltage source (see ). VREF Circuit Built-in Power Supply and Voltage Reference The VREF module for the MSPM0G family is a shared voltage reference module that can be leveraged by a variety on on-board analog peripherals. The VREF module features include: 1.4-V and 2.5-V user-selectable internal references. Support for receiving external reference on the VREF+ and VREF- device pins. Sample and hold mode support VREF operation down to STANDBY operating mode. Internal reference supports for ADC, COMP, and OPA. When supplying the MCU with an external reference, TI recommends connecting a decoupling capacitor on the reference pins with a value based on the voltage source (see ). VREF Circuit The VREF module for the MSPM0G family is a shared voltage reference module that can be leveraged by a variety on on-board analog peripherals. The VREF module features include: 1.4-V and 2.5-V user-selectable internal references. Support for receiving external reference on the VREF+ and VREF- device pins. Sample and hold mode support VREF operation down to STANDBY operating mode. Internal reference supports for ADC, COMP, and OPA. When supplying the MCU with an external reference, TI recommends connecting a decoupling capacitor on the reference pins with a value based on the voltage source (see ). VREF Circuit The VREF module for the MSPM0G family is a shared voltage reference module that can be leveraged by a variety on on-board analog peripherals.The VREF module features include: 1.4-V and 2.5-V user-selectable internal references. Support for receiving external reference on the VREF+ and VREF- device pins. Sample and hold mode support VREF operation down to STANDBY operating mode. Internal reference supports for ADC, COMP, and OPA. 1.4-V and 2.5-V user-selectable internal references.Support for receiving external reference on the VREF+ and VREF- device pins.Sample and hold mode support VREF operation down to STANDBY operating mode.Internal reference supports for ADC, COMP, and OPA.When supplying the MCU with an external reference, TI recommends connecting a decoupling capacitor on the reference pins with a value based on the voltage source (see ). VREF Circuit VREF Circuit Recommended Decoupling Circuit for Power Supply TI recommends connecting a combination of a 10-μF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC pin (see ). Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Power Supply Decoupling Circuit Recommended Decoupling Circuit for Power Supply TI recommends connecting a combination of a 10-μF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC pin (see ). Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Power Supply Decoupling Circuit TI recommends connecting a combination of a 10-μF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC pin (see ). Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Power Supply Decoupling Circuit TI recommends connecting a combination of a 10-μF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC pin (see ). Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Power Supply Decoupling Circuit Power Supply Decoupling Circuit Reset and Power Supply Supervisor Digital Power Supply The device has five reset levels: Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) The details of the relationships between reset levels is described in the Technical Reference Manual (TRM). After a cold start, the NRST pin is configured in NRST mode. The NRST pin must be high for the device to boot successfully. There is no internal pullup resistor on NRST. External circuitry (either a pullup resistor to DVCC or a reset control circuit) must actively pull NRST high for the device to start. A capacitor and an open button are needed for manual reset (see ). After the device is started, a low pulse on NRST that is <1 second in duration triggers a BOOTRST. If a low pulse on NRST longer than 1 second triggers a POR. NRST Recommended Circuit Power Supply Supervisor Power-on Reset (POR) Monitor The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state. The POR monitor does not indicate that VDD has reached a level high enough to support correct operation of the device. Rather, it is the first step in the boot process and is used to determine if the supply voltage is sufficient to power up the bandgap reference and BOR circuit, which are then used to determine if the supply has reached a level sufficient to for the device to run correctly. The POR monitor is active in all power modes including SHUTDOWN, and cannot be disabled. (The POR triggered waveform is shown in ). Brownout Reset (BOR) Monitor The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator.The BOR threshold reference is derived from the internal bandgap circuit. The threshold itself is programmable and is always higher than the POR threshold. During cold start, after VDD passes the POR+ threshold the bandgap reference and BOR circuit are started. The device is then held in a BOR state until VDD passes the BOR0+ threshold. Once VDD passes BOR0+, the BOR monitor releases the device to continue the boot process, and the PMU is started. (The BOR triggered waveform is shown in ). POR and BOR Behavior During Supply Changes When the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD which do not pass below the BOR0- threshold do not cause a BOR- violation, and the device will continue to run. The BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset. POR and BOR vs. Supply Voltage (VDD) Reset and Power Supply Supervisor Digital Power Supply The device has five reset levels: Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) The details of the relationships between reset levels is described in the Technical Reference Manual (TRM). After a cold start, the NRST pin is configured in NRST mode. The NRST pin must be high for the device to boot successfully. There is no internal pullup resistor on NRST. External circuitry (either a pullup resistor to DVCC or a reset control circuit) must actively pull NRST high for the device to start. A capacitor and an open button are needed for manual reset (see ). After the device is started, a low pulse on NRST that is <1 second in duration triggers a BOOTRST. If a low pulse on NRST longer than 1 second triggers a POR. NRST Recommended Circuit Digital Power Supply The device has five reset levels: Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) The details of the relationships between reset levels is described in the Technical Reference Manual (TRM). After a cold start, the NRST pin is configured in NRST mode. The NRST pin must be high for the device to boot successfully. There is no internal pullup resistor on NRST. External circuitry (either a pullup resistor to DVCC or a reset control circuit) must actively pull NRST high for the device to start. A capacitor and an open button are needed for manual reset (see ). After the device is started, a low pulse on NRST that is <1 second in duration triggers a BOOTRST. If a low pulse on NRST longer than 1 second triggers a POR. NRST Recommended Circuit The device has five reset levels: Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) The details of the relationships between reset levels is described in the Technical Reference Manual (TRM). After a cold start, the NRST pin is configured in NRST mode. The NRST pin must be high for the device to boot successfully. There is no internal pullup resistor on NRST. External circuitry (either a pullup resistor to DVCC or a reset control circuit) must actively pull NRST high for the device to start. A capacitor and an open button are needed for manual reset (see ). After the device is started, a low pulse on NRST that is <1 second in duration triggers a BOOTRST. If a low pulse on NRST longer than 1 second triggers a POR. NRST Recommended Circuit The device has five reset levels: Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) The details of the relationships between reset levels is described in the Technical Reference Manual (TRM). Power-on reset (POR) Brownout reset (BOR) Boot reset (BOOTRST) System reset (SYSRST) CPU reset (CPURST) Power-on reset (POR)Brownout reset (BOR)Boot reset (BOOTRST)System reset (SYSRST)CPU reset (CPURST)After a cold start, the NRST pin is configured in NRST mode. The NRST pin must be high for the device to boot successfully. There is no internal pullup resistor on NRST. External circuitry (either a pullup resistor to DVCC or a reset control circuit) must actively pull NRST high for the device to start. A capacitor and an open button are needed for manual reset (see ). After the device is started, a low pulse on NRST that is <1 second in duration triggers a BOOTRST. If a low pulse on NRST longer than 1 second triggers a POR. NRST Recommended Circuit NRST Recommended Circuit Power Supply Supervisor Power-on Reset (POR) Monitor The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state. The POR monitor does not indicate that VDD has reached a level high enough to support correct operation of the device. Rather, it is the first step in the boot process and is used to determine if the supply voltage is sufficient to power up the bandgap reference and BOR circuit, which are then used to determine if the supply has reached a level sufficient to for the device to run correctly. The POR monitor is active in all power modes including SHUTDOWN, and cannot be disabled. (The POR triggered waveform is shown in ). Brownout Reset (BOR) Monitor The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator.The BOR threshold reference is derived from the internal bandgap circuit. The threshold itself is programmable and is always higher than the POR threshold. During cold start, after VDD passes the POR+ threshold the bandgap reference and BOR circuit are started. The device is then held in a BOR state until VDD passes the BOR0+ threshold. Once VDD passes BOR0+, the BOR monitor releases the device to continue the boot process, and the PMU is started. (The BOR triggered waveform is shown in ). POR and BOR Behavior During Supply Changes When the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD which do not pass below the BOR0- threshold do not cause a BOR- violation, and the device will continue to run. The BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset. POR and BOR vs. Supply Voltage (VDD) Power Supply Supervisor Power-on Reset (POR) Monitor The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state. The POR monitor does not indicate that VDD has reached a level high enough to support correct operation of the device. Rather, it is the first step in the boot process and is used to determine if the supply voltage is sufficient to power up the bandgap reference and BOR circuit, which are then used to determine if the supply has reached a level sufficient to for the device to run correctly. The POR monitor is active in all power modes including SHUTDOWN, and cannot be disabled. (The POR triggered waveform is shown in ). Brownout Reset (BOR) Monitor The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator.The BOR threshold reference is derived from the internal bandgap circuit. The threshold itself is programmable and is always higher than the POR threshold. During cold start, after VDD passes the POR+ threshold the bandgap reference and BOR circuit are started. The device is then held in a BOR state until VDD passes the BOR0+ threshold. Once VDD passes BOR0+, the BOR monitor releases the device to continue the boot process, and the PMU is started. (The BOR triggered waveform is shown in ). POR and BOR Behavior During Supply Changes When the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD which do not pass below the BOR0- threshold do not cause a BOR- violation, and the device will continue to run. The BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset. POR and BOR vs. Supply Voltage (VDD) Power-on Reset (POR) Monitor The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state. The POR monitor does not indicate that VDD has reached a level high enough to support correct operation of the device. Rather, it is the first step in the boot process and is used to determine if the supply voltage is sufficient to power up the bandgap reference and BOR circuit, which are then used to determine if the supply has reached a level sufficient to for the device to run correctly. The POR monitor is active in all power modes including SHUTDOWN, and cannot be disabled. (The POR triggered waveform is shown in ). Power-on Reset (POR) Monitor The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state. The power-on reset (POR) monitor supervises the external supply (VDD) and asserts or de-asserts a POR violation to SYSCTL. During cold power-up, the device is held in a POR state until VDD passes the POR+. Once VDD has passed POR+, the POR state is released and the bandgap reference and BOR monitor circuit are started. If VDD drops below the POR- level, then a POR- violation is asserted and the device is again held in a POR reset state.The POR monitor does not indicate that VDD has reached a level high enough to support correct operation of the device. Rather, it is the first step in the boot process and is used to determine if the supply voltage is sufficient to power up the bandgap reference and BOR circuit, which are then used to determine if the supply has reached a level sufficient to for the device to run correctly. The POR monitor is active in all power modes including SHUTDOWN, and cannot be disabled. (The POR triggered waveform is shown in ). Brownout Reset (BOR) Monitor The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator.The BOR threshold reference is derived from the internal bandgap circuit. The threshold itself is programmable and is always higher than the POR threshold. During cold start, after VDD passes the POR+ threshold the bandgap reference and BOR circuit are started. The device is then held in a BOR state until VDD passes the BOR0+ threshold. Once VDD passes BOR0+, the BOR monitor releases the device to continue the boot process, and the PMU is started. (The BOR triggered waveform is shown in ). Brownout Reset (BOR) Monitor The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator.The BOR threshold reference is derived from the internal bandgap circuit. The threshold itself is programmable and is always higher than the POR threshold. During cold start, after VDD passes the POR+ threshold the bandgap reference and BOR circuit are started. The device is then held in a BOR state until VDD passes the BOR0+ threshold. Once VDD passes BOR0+, the BOR monitor releases the device to continue the boot process, and the PMU is started. (The BOR triggered waveform is shown in ).The brownout reset (BOR) monitor supervises the external supply (VDD) and asserts or de-asserts a BOR violation to SYSCTL. The primary responsibility of the BOR circuit is to ensure that the external supply is maintained high enough to enable correct operation of internal circuits, including the core regulator. POR and BOR Behavior During Supply Changes When the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD which do not pass below the BOR0- threshold do not cause a BOR- violation, and the device will continue to run. The BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset. POR and BOR vs. Supply Voltage (VDD) POR and BOR Behavior During Supply ChangesWhen the supply voltage (VDD) drops below POR-, the entire device state is cleared. Small variations in VDD which do not pass below the BOR0- threshold do not cause a BOR- violation, and the device will continue to run. The BOR circuit is configured to generate an interrupt rather than immediately triggering a BOR reset. POR and BOR vs. Supply Voltage (VDD) POR and BOR vs. Supply Voltage (VDD) Clock System The clock system of MSPM0G series contains the internal oscillators, the clock monitors, and the clock selection and control logic. This section describes the clock resources on different MSPM0G family devices and their interaction with external signals or devices. Internal Oscillators Internal Low-Frequency Oscillator (LFOSC) LFOSC is an on-chip low power oscillator that is factory trimmed to a frequency of 32.768 kHz. It provides a low-frequency clock that can be used to help the system achieve low power consumption. The LFOSC can provide higher accuracy when used over a reduced temperature range. See the device-specific data sheet for details. MSPM0G Series LFOSC Internal System Oscillator (SYSOSC) SYSOSC is an on-chip, accurate, and configurable oscillator with factory-trimmed frequencies of 32 MHz (base frequency) and 4 MHz (low frequency), as well as support for user-trimmed operation at either 24 MHz or 16 MHz. It provides a high frequency clock that allows the CPU to run at high speed for executing code and processing performance. MSPM0G Series SYSOSC SYSOSC Frequency Correction Loop The additional hardware setting for this oscillator is an external resistor, populated between the ROSC pin and VSS, to increase SYSOSC from a base accuracy of ±2.5% across temperature. The overall SYSOSC application accuracy is determined by combining the following error sources to determine the total error: The ROSC reference resistor error (due to tolerance and temperature drift) The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) #GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB shows how to calculate the SYSOSC application accuracy for two different ROSC resistor specs across two temperature ranges. For more details, see the device-specific TRM. SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA) Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% System Phase-Locked Loop (SYSPLL) SYSPLL is the system phase-locked loop with programmable frequency and is used to achieve the MSPM0G series highest speed (80 MHz). MSPM0G SYSPLL Circuit External Oscillators For applications that require even higher clock accuracy across devices and temperature, external oscillators can be used. LFXT can replace LFOSC, and HFXT can replace SYSOSC. Low-Frequency Crystal Oscillator (LFXT) The LFXT is an ultra-low power crystal oscillator that supports driving a standard 32.768-kHz watch crystal. To use the LFXT, populate a watch crystal between the LFXIN and LFXOUT pins. Place loading capacitors on both LFXIN and LFXOUT pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A variety of crystal types are supported through a programmable drive strength mechanism. For the layout advice, see . MSPM0G LFXT Circuit LFCLK_IN (Digital Clock) The LFXT circuit can be bypassed and a 32.76-kHz typical frequency digital clock can be brought into the device to use as the LFCLK source. LFCLK_IN and LFXT are mutually exclusive and must not be enabled at the same time. LFCLK_IN is compatible with digital square-wave CMOS clock inputs with a typical duty cycle of 50%. It is possible to check for a valid clock signal on LFCLK_IN by enabling the LFCLK monitor. By default, the LFCLK monitor checks LFCLK_IN if the LFXT was not started. High-Frequency Crystal Oscillator (HFXT) The high frequency crystal oscillator (HFXT) can be used with standard crystals and resonators in the 4- to 48-MHz range to generate a stable high-speed reference clock for the system. To use the HFXT, populate a crystal or resonator between the HFXIN and HFXOUT pins. Place loading capacitors on both pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A programmable HFXT startup time is provided with 64-µs resolution. For layout advice, see . MSPM0G HFXT Circuit HFCLK_IN (Digital clock) It is possible to bypass the HFXT circuit and bring in a 4- to 48-MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. HFCLK_IN and HFXT are mutually exclusive and must not be enabled at the same time. HFCLK_IN is compatible with digital square wave CMOS clock inputs with a typical duty cycle of 50%. External Clock Output (CLK_OUT) A clock output unit can send digital clocks from the device to external circuits or to the frequency clock counter. This feature is useful for clocking external circuitry such as an external ADC that does not have its own clock source. The clock output unit has a flexible set of sources to select, and it includes a programmable divider. MSPM0G External Clock Output Available clock sources for CLK_OUT: SYSPLLCLK1 HFCLK SYSOSC ULPCLK MFCLK LFCLK The selected clock source can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 before being output to the pin or to the frequency clock counter. Frequency Clock Counter (FCC) The frequency clock counter (FCC) enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected source clock within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock. MSPM0G Frequency Clock Counter Block Diagram Application software can use the FCC to measure the frequency of the following oscillators and clocks: MCLK SYSOSC HFCLK CLK_OUT SYSPLLCLK0 SYSPLLCLK1 SYSPLLCLK2X The external FCC input (FCC_IN) While the external FCC input (FCC_IN function) can be used as either the FCC clock source or the FCC trigger input, it cannot be used for both functions during the same FCC capture. It must be configured as either the FCC clock source or the FCC trigger. Clock System The clock system of MSPM0G series contains the internal oscillators, the clock monitors, and the clock selection and control logic. This section describes the clock resources on different MSPM0G family devices and their interaction with external signals or devices. The clock system of MSPM0G series contains the internal oscillators, the clock monitors, and the clock selection and control logic. This section describes the clock resources on different MSPM0G family devices and their interaction with external signals or devices. Internal Oscillators Internal Low-Frequency Oscillator (LFOSC) LFOSC is an on-chip low power oscillator that is factory trimmed to a frequency of 32.768 kHz. It provides a low-frequency clock that can be used to help the system achieve low power consumption. The LFOSC can provide higher accuracy when used over a reduced temperature range. See the device-specific data sheet for details. MSPM0G Series LFOSC Internal System Oscillator (SYSOSC) SYSOSC is an on-chip, accurate, and configurable oscillator with factory-trimmed frequencies of 32 MHz (base frequency) and 4 MHz (low frequency), as well as support for user-trimmed operation at either 24 MHz or 16 MHz. It provides a high frequency clock that allows the CPU to run at high speed for executing code and processing performance. MSPM0G Series SYSOSC SYSOSC Frequency Correction Loop The additional hardware setting for this oscillator is an external resistor, populated between the ROSC pin and VSS, to increase SYSOSC from a base accuracy of ±2.5% across temperature. The overall SYSOSC application accuracy is determined by combining the following error sources to determine the total error: The ROSC reference resistor error (due to tolerance and temperature drift) The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) #GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB shows how to calculate the SYSOSC application accuracy for two different ROSC resistor specs across two temperature ranges. For more details, see the device-specific TRM. SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA) Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% System Phase-Locked Loop (SYSPLL) SYSPLL is the system phase-locked loop with programmable frequency and is used to achieve the MSPM0G series highest speed (80 MHz). MSPM0G SYSPLL Circuit Internal Oscillators Internal Low-Frequency Oscillator (LFOSC) LFOSC is an on-chip low power oscillator that is factory trimmed to a frequency of 32.768 kHz. It provides a low-frequency clock that can be used to help the system achieve low power consumption. The LFOSC can provide higher accuracy when used over a reduced temperature range. See the device-specific data sheet for details. MSPM0G Series LFOSC Internal System Oscillator (SYSOSC) SYSOSC is an on-chip, accurate, and configurable oscillator with factory-trimmed frequencies of 32 MHz (base frequency) and 4 MHz (low frequency), as well as support for user-trimmed operation at either 24 MHz or 16 MHz. It provides a high frequency clock that allows the CPU to run at high speed for executing code and processing performance. MSPM0G Series SYSOSC SYSOSC Frequency Correction Loop The additional hardware setting for this oscillator is an external resistor, populated between the ROSC pin and VSS, to increase SYSOSC from a base accuracy of ±2.5% across temperature. The overall SYSOSC application accuracy is determined by combining the following error sources to determine the total error: The ROSC reference resistor error (due to tolerance and temperature drift) The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) #GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB shows how to calculate the SYSOSC application accuracy for two different ROSC resistor specs across two temperature ranges. For more details, see the device-specific TRM. SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA) Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% System Phase-Locked Loop (SYSPLL) SYSPLL is the system phase-locked loop with programmable frequency and is used to achieve the MSPM0G series highest speed (80 MHz). MSPM0G SYSPLL Circuit Internal Low-Frequency Oscillator (LFOSC) LFOSC is an on-chip low power oscillator that is factory trimmed to a frequency of 32.768 kHz. It provides a low-frequency clock that can be used to help the system achieve low power consumption. The LFOSC can provide higher accuracy when used over a reduced temperature range. See the device-specific data sheet for details. MSPM0G Series LFOSC Internal Low-Frequency Oscillator (LFOSC)LFOSC is an on-chip low power oscillator that is factory trimmed to a frequency of 32.768 kHz. It provides a low-frequency clock that can be used to help the system achieve low power consumption. The LFOSC can provide higher accuracy when used over a reduced temperature range. See the device-specific data sheet for details. MSPM0G Series LFOSC MSPM0G Series LFOSC Internal System Oscillator (SYSOSC) SYSOSC is an on-chip, accurate, and configurable oscillator with factory-trimmed frequencies of 32 MHz (base frequency) and 4 MHz (low frequency), as well as support for user-trimmed operation at either 24 MHz or 16 MHz. It provides a high frequency clock that allows the CPU to run at high speed for executing code and processing performance. MSPM0G Series SYSOSC SYSOSC Frequency Correction Loop The additional hardware setting for this oscillator is an external resistor, populated between the ROSC pin and VSS, to increase SYSOSC from a base accuracy of ±2.5% across temperature. The overall SYSOSC application accuracy is determined by combining the following error sources to determine the total error: The ROSC reference resistor error (due to tolerance and temperature drift) The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) #GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB shows how to calculate the SYSOSC application accuracy for two different ROSC resistor specs across two temperature ranges. For more details, see the device-specific TRM. SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA) Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% System Phase-Locked Loop (SYSPLL) SYSPLL is the system phase-locked loop with programmable frequency and is used to achieve the MSPM0G series highest speed (80 MHz). MSPM0G SYSPLL Circuit Internal System Oscillator (SYSOSC)SYSOSC is an on-chip, accurate, and configurable oscillator with factory-trimmed frequencies of 32 MHz (base frequency) and 4 MHz (low frequency), as well as support for user-trimmed operation at either 24 MHz or 16 MHz. It provides a high frequency clock that allows the CPU to run at high speed for executing code and processing performance. MSPM0G Series SYSOSC MSPM0G Series SYSOSC SYSOSC Frequency Correction Loop SYSOSC Frequency Correction LoopThe additional hardware setting for this oscillator is an external resistor, populated between the ROSC pin and VSS, to increase SYSOSC from a base accuracy of ±2.5% across temperature.The overall SYSOSC application accuracy is determined by combining the following error sources to determine the total error: The ROSC reference resistor error (due to tolerance and temperature drift) The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) The ROSC reference resistor error (due to tolerance and temperature drift)The SYSOSC circuit error in FCL mode (±0.75% for -40°C to 85°C or ±0.90% for -40°C to 125°C) #GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB shows how to calculate the SYSOSC application accuracy for two different ROSC resistor specs across two temperature ranges. For more details, see the device-specific TRM.#GUID-F6D46FF3-4736-45DA-95BB-BE7E97053995/GUID-F6EEBED2-F653-4C16-A93E-B1BFC9DF65CB SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA) Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% SYSOSC Accuracy With FCL, by ROSC Tolerance, RSOC TCR, and Ambient Temperature (TA)A Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C Ambient Temperature (TA) -40 ≤ TA ≤ 125°C -40 ≤ TA ≤ 85°C Ambient Temperature (TA)A-40 ≤ TA ≤ 125°C A-40 ≤ TA ≤ 85°C A ROSC Resistor Parameters ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ±0.1% 25 ppm/°C ±0.5% 25 ppm/°C ROSC Resistor Parameters±0.1% 25 ppm/°C±0.5% 25 ppm/°C±0.1% 25 ppm/°C±0.5% 25 ppm/°C Nominal ROSC resistance (ROSCnom) 100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% Nominal ROSC resistance (ROSCnom) 100 kΩ Nominal ROSC resistance (ROSCnom)nom100 kΩ Maximum ROSC resistance (at 25°C) 100.1 kΩ 100.5 kΩ 100.1 kΩ 100.5 kΩ Maximum ROSC resistance (at 25°C)100.1 kΩ100.5 kΩ100.1 kΩ100.5 kΩ Minimum ROSC resistance (at 25°C) 99.9 kΩ 99.5 kΩ 99.9 kΩ 99.5 kΩ Minimum ROSC resistance (at 25°C)99.9 kΩ99.5 kΩ99.9 kΩ99.5 kΩ ROSC resistor TCR 25 ppm/°C ROSC resistor TCR25 ppm/°C ROSC temperature drift -0.16% to 0.25% -0.16% to 0.15% ROSC temperature drift-0.16% to 0.25%-0.16% to 0.15% Maximum ROSC resistance (at high temperature) (ROSCmax) 100.35 kΩ 100.75 kΩ 100.25 kΩ 100.65 kΩ Maximum ROSC resistance (at high temperature) (ROSCmax)max100.35 kΩ100.75 kΩ100.25 kΩ100.65 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin) 99.74 kΩ 99.34 kΩ 99.74 kΩ 99.34 kΩ Minimum ROSC resistance (at low temperature) (ROSCmin)min99.74 kΩ99.34 kΩ99.74 kΩ99.34 kΩ ROSC resistance error (high temperature) (ROSCerr+) +0.35% +0.75% + 0.25% +0.65% ROSC resistance error (high temperature) (ROSCerr+)err+ +0.35% +0.75%+ 0.25%+0.65% ROSC resistance error (low temperature) (ROSCerr-) -0.26% -0.66% -0.26% -0.66% ROSC resistance error (low temperature) (ROSCerr-)err--0.26%-0.66%-0.26%-0.66% SYSOSC circuit error (SYSOSCerr) ±0.9% ±0.75% SYSOSC circuit error (SYSOSCerr)err±0.9%±0.75% Total accuracy (TOTerr-, TOTerr+) -1.2% to +1.3% -1.6% to +1.7% -1.0% to +1.0% -1.4% to +1.4% Total accuracy (TOTerr-, TOTerr+)err-err+-1.2% to +1.3%-1.6% to +1.7%-1.0% to +1.0%-1.4% to +1.4% System Phase-Locked Loop (SYSPLL) System Phase-Locked Loop (SYSPLL)SYSPLL is the system phase-locked loop with programmable frequency and is used to achieve the MSPM0G series highest speed (80 MHz). MSPM0G SYSPLL Circuit MSPM0G SYSPLL Circuit External Oscillators For applications that require even higher clock accuracy across devices and temperature, external oscillators can be used. LFXT can replace LFOSC, and HFXT can replace SYSOSC. Low-Frequency Crystal Oscillator (LFXT) The LFXT is an ultra-low power crystal oscillator that supports driving a standard 32.768-kHz watch crystal. To use the LFXT, populate a watch crystal between the LFXIN and LFXOUT pins. Place loading capacitors on both LFXIN and LFXOUT pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A variety of crystal types are supported through a programmable drive strength mechanism. For the layout advice, see . MSPM0G LFXT Circuit LFCLK_IN (Digital Clock) The LFXT circuit can be bypassed and a 32.76-kHz typical frequency digital clock can be brought into the device to use as the LFCLK source. LFCLK_IN and LFXT are mutually exclusive and must not be enabled at the same time. LFCLK_IN is compatible with digital square-wave CMOS clock inputs with a typical duty cycle of 50%. It is possible to check for a valid clock signal on LFCLK_IN by enabling the LFCLK monitor. By default, the LFCLK monitor checks LFCLK_IN if the LFXT was not started. High-Frequency Crystal Oscillator (HFXT) The high frequency crystal oscillator (HFXT) can be used with standard crystals and resonators in the 4- to 48-MHz range to generate a stable high-speed reference clock for the system. To use the HFXT, populate a crystal or resonator between the HFXIN and HFXOUT pins. Place loading capacitors on both pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A programmable HFXT startup time is provided with 64-µs resolution. For layout advice, see . MSPM0G HFXT Circuit HFCLK_IN (Digital clock) It is possible to bypass the HFXT circuit and bring in a 4- to 48-MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. HFCLK_IN and HFXT are mutually exclusive and must not be enabled at the same time. HFCLK_IN is compatible with digital square wave CMOS clock inputs with a typical duty cycle of 50%. External Oscillators For applications that require even higher clock accuracy across devices and temperature, external oscillators can be used. LFXT can replace LFOSC, and HFXT can replace SYSOSC. Low-Frequency Crystal Oscillator (LFXT) The LFXT is an ultra-low power crystal oscillator that supports driving a standard 32.768-kHz watch crystal. To use the LFXT, populate a watch crystal between the LFXIN and LFXOUT pins. Place loading capacitors on both LFXIN and LFXOUT pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A variety of crystal types are supported through a programmable drive strength mechanism. For the layout advice, see . MSPM0G LFXT Circuit LFCLK_IN (Digital Clock) The LFXT circuit can be bypassed and a 32.76-kHz typical frequency digital clock can be brought into the device to use as the LFCLK source. LFCLK_IN and LFXT are mutually exclusive and must not be enabled at the same time. LFCLK_IN is compatible with digital square-wave CMOS clock inputs with a typical duty cycle of 50%. It is possible to check for a valid clock signal on LFCLK_IN by enabling the LFCLK monitor. By default, the LFCLK monitor checks LFCLK_IN if the LFXT was not started. High-Frequency Crystal Oscillator (HFXT) The high frequency crystal oscillator (HFXT) can be used with standard crystals and resonators in the 4- to 48-MHz range to generate a stable high-speed reference clock for the system. To use the HFXT, populate a crystal or resonator between the HFXIN and HFXOUT pins. Place loading capacitors on both pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A programmable HFXT startup time is provided with 64-µs resolution. For layout advice, see . MSPM0G HFXT Circuit HFCLK_IN (Digital clock) It is possible to bypass the HFXT circuit and bring in a 4- to 48-MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. HFCLK_IN and HFXT are mutually exclusive and must not be enabled at the same time. HFCLK_IN is compatible with digital square wave CMOS clock inputs with a typical duty cycle of 50%. For applications that require even higher clock accuracy across devices and temperature, external oscillators can be used. LFXT can replace LFOSC, and HFXT can replace SYSOSC. For applications that require even higher clock accuracy across devices and temperature, external oscillators can be used. LFXT can replace LFOSC, and HFXT can replace SYSOSC. Low-Frequency Crystal Oscillator (LFXT) The LFXT is an ultra-low power crystal oscillator that supports driving a standard 32.768-kHz watch crystal. To use the LFXT, populate a watch crystal between the LFXIN and LFXOUT pins. Place loading capacitors on both LFXIN and LFXOUT pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A variety of crystal types are supported through a programmable drive strength mechanism. For the layout advice, see . MSPM0G LFXT Circuit LFCLK_IN (Digital Clock) The LFXT circuit can be bypassed and a 32.76-kHz typical frequency digital clock can be brought into the device to use as the LFCLK source. LFCLK_IN and LFXT are mutually exclusive and must not be enabled at the same time. LFCLK_IN is compatible with digital square-wave CMOS clock inputs with a typical duty cycle of 50%. It is possible to check for a valid clock signal on LFCLK_IN by enabling the LFCLK monitor. By default, the LFCLK monitor checks LFCLK_IN if the LFXT was not started. Low-Frequency Crystal Oscillator (LFXT)The LFXT is an ultra-low power crystal oscillator that supports driving a standard 32.768-kHz watch crystal. To use the LFXT, populate a watch crystal between the LFXIN and LFXOUT pins. Place loading capacitors on both LFXIN and LFXOUT pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A variety of crystal types are supported through a programmable drive strength mechanism. For the layout advice, see . MSPM0G LFXT Circuit MSPM0G LFXT Circuit LFCLK_IN (Digital Clock) LFCLK_IN (Digital Clock)The LFXT circuit can be bypassed and a 32.76-kHz typical frequency digital clock can be brought into the device to use as the LFCLK source. LFCLK_IN and LFXT are mutually exclusive and must not be enabled at the same time.LFCLK_IN is compatible with digital square-wave CMOS clock inputs with a typical duty cycle of 50%. It is possible to check for a valid clock signal on LFCLK_IN by enabling the LFCLK monitor. By default, the LFCLK monitor checks LFCLK_IN if the LFXT was not started. High-Frequency Crystal Oscillator (HFXT) The high frequency crystal oscillator (HFXT) can be used with standard crystals and resonators in the 4- to 48-MHz range to generate a stable high-speed reference clock for the system. To use the HFXT, populate a crystal or resonator between the HFXIN and HFXOUT pins. Place loading capacitors on both pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A programmable HFXT startup time is provided with 64-µs resolution. For layout advice, see . MSPM0G HFXT Circuit HFCLK_IN (Digital clock) It is possible to bypass the HFXT circuit and bring in a 4- to 48-MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. HFCLK_IN and HFXT are mutually exclusive and must not be enabled at the same time. HFCLK_IN is compatible with digital square wave CMOS clock inputs with a typical duty cycle of 50%. High-Frequency Crystal Oscillator (HFXT)The high frequency crystal oscillator (HFXT) can be used with standard crystals and resonators in the 4- to 48-MHz range to generate a stable high-speed reference clock for the system.To use the HFXT, populate a crystal or resonator between the HFXIN and HFXOUT pins. Place loading capacitors on both pins to circuit ground (VSS). Size the crystal load capacitors according to the specifications of the crystal being used. A programmable HFXT startup time is provided with 64-µs resolution. For layout advice, see . MSPM0G HFXT Circuit MSPM0G HFXT Circuit HFCLK_IN (Digital clock) HFCLK_IN (Digital clock)It is possible to bypass the HFXT circuit and bring in a 4- to 48-MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. HFCLK_IN and HFXT are mutually exclusive and must not be enabled at the same time.HFCLK_IN is compatible with digital square wave CMOS clock inputs with a typical duty cycle of 50%. External Clock Output (CLK_OUT) A clock output unit can send digital clocks from the device to external circuits or to the frequency clock counter. This feature is useful for clocking external circuitry such as an external ADC that does not have its own clock source. The clock output unit has a flexible set of sources to select, and it includes a programmable divider. MSPM0G External Clock Output Available clock sources for CLK_OUT: SYSPLLCLK1 HFCLK SYSOSC ULPCLK MFCLK LFCLK The selected clock source can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 before being output to the pin or to the frequency clock counter. External Clock Output (CLK_OUT) A clock output unit can send digital clocks from the device to external circuits or to the frequency clock counter. This feature is useful for clocking external circuitry such as an external ADC that does not have its own clock source. The clock output unit has a flexible set of sources to select, and it includes a programmable divider. MSPM0G External Clock Output Available clock sources for CLK_OUT: SYSPLLCLK1 HFCLK SYSOSC ULPCLK MFCLK LFCLK The selected clock source can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 before being output to the pin or to the frequency clock counter. A clock output unit can send digital clocks from the device to external circuits or to the frequency clock counter. This feature is useful for clocking external circuitry such as an external ADC that does not have its own clock source. The clock output unit has a flexible set of sources to select, and it includes a programmable divider. MSPM0G External Clock Output Available clock sources for CLK_OUT: SYSPLLCLK1 HFCLK SYSOSC ULPCLK MFCLK LFCLK The selected clock source can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 before being output to the pin or to the frequency clock counter. A clock output unit can send digital clocks from the device to external circuits or to the frequency clock counter. This feature is useful for clocking external circuitry such as an external ADC that does not have its own clock source. The clock output unit has a flexible set of sources to select, and it includes a programmable divider. MSPM0G External Clock Output MSPM0G External Clock OutputAvailable clock sources for CLK_OUT: SYSPLLCLK1 HFCLK SYSOSC ULPCLK MFCLK LFCLK SYSPLLCLK1HFCLKSYSOSCULPCLKMFCLKLFCLKThe selected clock source can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 before being output to the pin or to the frequency clock counter. Frequency Clock Counter (FCC) The frequency clock counter (FCC) enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected source clock within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock. MSPM0G Frequency Clock Counter Block Diagram Application software can use the FCC to measure the frequency of the following oscillators and clocks: MCLK SYSOSC HFCLK CLK_OUT SYSPLLCLK0 SYSPLLCLK1 SYSPLLCLK2X The external FCC input (FCC_IN) While the external FCC input (FCC_IN function) can be used as either the FCC clock source or the FCC trigger input, it cannot be used for both functions during the same FCC capture. It must be configured as either the FCC clock source or the FCC trigger. Frequency Clock Counter (FCC) The frequency clock counter (FCC) enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected source clock within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock. MSPM0G Frequency Clock Counter Block Diagram Application software can use the FCC to measure the frequency of the following oscillators and clocks: MCLK SYSOSC HFCLK CLK_OUT SYSPLLCLK0 SYSPLLCLK1 SYSPLLCLK2X The external FCC input (FCC_IN) While the external FCC input (FCC_IN function) can be used as either the FCC clock source or the FCC trigger input, it cannot be used for both functions during the same FCC capture. It must be configured as either the FCC clock source or the FCC trigger. The frequency clock counter (FCC) enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected source clock within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock. MSPM0G Frequency Clock Counter Block Diagram Application software can use the FCC to measure the frequency of the following oscillators and clocks: MCLK SYSOSC HFCLK CLK_OUT SYSPLLCLK0 SYSPLLCLK1 SYSPLLCLK2X The external FCC input (FCC_IN) While the external FCC input (FCC_IN function) can be used as either the FCC clock source or the FCC trigger input, it cannot be used for both functions during the same FCC capture. It must be configured as either the FCC clock source or the FCC trigger. The frequency clock counter (FCC) enables flexible in-system testing and calibration of a variety of oscillators and clocks on the device. The FCC counts the number of clock periods seen on the selected source clock within a known fixed trigger period (derived from a secondary reference source) to provide an estimation of the frequency of the source clock. MSPM0G Frequency Clock Counter Block Diagram MSPM0G Frequency Clock Counter Block DiagramApplication software can use the FCC to measure the frequency of the following oscillators and clocks: MCLK SYSOSC HFCLK CLK_OUT SYSPLLCLK0 SYSPLLCLK1 SYSPLLCLK2X The external FCC input (FCC_IN) MCLKSYSOSCHFCLKCLK_OUTSYSPLLCLK0SYSPLLCLK1SYSPLLCLK2XThe external FCC input (FCC_IN)While the external FCC input (FCC_IN function) can be used as either the FCC clock source or the FCC trigger input, it cannot be used for both functions during the same FCC capture. It must be configured as either the FCC clock source or the FCC trigger. Debugger The debug subsystem (DEBUGSS) interfaces the serial wire debug (SWD) two-wire physical interface to multiple debug functions within the device. MSPM0G devices support debugging of processor execution, the device state, and the power state (using EnergyTrace technology). Host to Target Device Connection Debug port pins and Pinout The debug port contains SWCLK and SWDIO (see ) which have internal pull-down and pull-up resistors (see ). The MSPM0G MCU family is offered in various packages with different numbers of available pins. See the data sheet for device-specific details. MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data MSPM0G SWD Internal Pull Debug Port Connection With Standard JTAG Connector The shows the connection between MSPM0G family MCU SWD debug port with the standard JTAG connector. JTAG and MSPM0G Connection For MSPM0G device, you can use XDS110 to implement debug/download function. Here list the contents of the XDS110 and provides instruction on installing the hardware. Standard XDS110 You can purchase a standard XDS110 on ti.com. shows a high-level diagram of the major functional areas and interfaces of the XDS110 probe. XDS110 Probe High-Level Block Diagram More standard XDS110 information, refer to the XDS110 Debug Probe User’s Guide. Lite XDS110 (MSPM0 LaunchPad Development Kit) The MSPM0 LaunchPad kit include XDS110-ET (Lite) circuit. You can use this debugger to download your firmware into MSPM0 device. shows XDS110-ET circuit. There are two probes in XDS110-ET: 2.54-mm probe: This port supports the SWD protocol and includes a 5-V or 3.3-V power supply. You can connect SWDIO SWCLK 3V3 GND to your board and download firmware into an MSPM0G device. And this probe also supports EnergyTrace technology to measure power consumption precisely in real time. More information for EnergyTrace technology, visit the EnergyTrace Technology tool page. XDS110-ET Circuit 10-pin probe: This port supports the JTAG and SWD protocols and includes a 3.3-V power supply. You can use a 10-pin cable to connect your board and XDS110-ET and download firmware into an MSPM0G device. show the 10-pin cable. Arm Standard 10-Pin Cable Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. Debugger The debug subsystem (DEBUGSS) interfaces the serial wire debug (SWD) two-wire physical interface to multiple debug functions within the device. MSPM0G devices support debugging of processor execution, the device state, and the power state (using EnergyTrace technology). Host to Target Device Connection The debug subsystem (DEBUGSS) interfaces the serial wire debug (SWD) two-wire physical interface to multiple debug functions within the device. MSPM0G devices support debugging of processor execution, the device state, and the power state (using EnergyTrace technology). Host to Target Device Connection Host to Target Device Connection Debug port pins and Pinout The debug port contains SWCLK and SWDIO (see ) which have internal pull-down and pull-up resistors (see ). The MSPM0G MCU family is offered in various packages with different numbers of available pins. See the data sheet for device-specific details. MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data MSPM0G SWD Internal Pull Debug port pins and Pinout The debug port contains SWCLK and SWDIO (see ) which have internal pull-down and pull-up resistors (see ). The MSPM0G MCU family is offered in various packages with different numbers of available pins. See the data sheet for device-specific details. MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data MSPM0G SWD Internal Pull The debug port contains SWCLK and SWDIO (see ) which have internal pull-down and pull-up resistors (see ). The MSPM0G MCU family is offered in various packages with different numbers of available pins. See the data sheet for device-specific details. MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data The debug port contains SWCLK and SWDIO (see ) which have internal pull-down and pull-up resistors (see ). The MSPM0G MCU family is offered in various packages with different numbers of available pins. See the data sheet for device-specific details. MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data MSPM0G Debug Ports DEVICE SIGNAL DERECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data DEVICE SIGNAL DERECTION SWD FUNCTION DEVICE SIGNAL DERECTION SWD FUNCTION DEVICE SIGNALDERECTIONSWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data SWCLK Input Serial wire clock from debug probe SWCLKInputSerial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data SWDIOInput/OutputBi-directional (shared) serial wire data MSPM0G SWD Internal Pull MSPM0G SWD Internal Pull MSPM0G SWD Internal Pull Debug Port Connection With Standard JTAG Connector The shows the connection between MSPM0G family MCU SWD debug port with the standard JTAG connector. JTAG and MSPM0G Connection For MSPM0G device, you can use XDS110 to implement debug/download function. Here list the contents of the XDS110 and provides instruction on installing the hardware. Standard XDS110 You can purchase a standard XDS110 on ti.com. shows a high-level diagram of the major functional areas and interfaces of the XDS110 probe. XDS110 Probe High-Level Block Diagram More standard XDS110 information, refer to the XDS110 Debug Probe User’s Guide. Lite XDS110 (MSPM0 LaunchPad Development Kit) The MSPM0 LaunchPad kit include XDS110-ET (Lite) circuit. You can use this debugger to download your firmware into MSPM0 device. shows XDS110-ET circuit. There are two probes in XDS110-ET: 2.54-mm probe: This port supports the SWD protocol and includes a 5-V or 3.3-V power supply. You can connect SWDIO SWCLK 3V3 GND to your board and download firmware into an MSPM0G device. And this probe also supports EnergyTrace technology to measure power consumption precisely in real time. More information for EnergyTrace technology, visit the EnergyTrace Technology tool page. XDS110-ET Circuit 10-pin probe: This port supports the JTAG and SWD protocols and includes a 3.3-V power supply. You can use a 10-pin cable to connect your board and XDS110-ET and download firmware into an MSPM0G device. show the 10-pin cable. Arm Standard 10-Pin Cable Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. Debug Port Connection With Standard JTAG Connector The shows the connection between MSPM0G family MCU SWD debug port with the standard JTAG connector. JTAG and MSPM0G Connection For MSPM0G device, you can use XDS110 to implement debug/download function. Here list the contents of the XDS110 and provides instruction on installing the hardware. Standard XDS110 You can purchase a standard XDS110 on ti.com. shows a high-level diagram of the major functional areas and interfaces of the XDS110 probe. XDS110 Probe High-Level Block Diagram More standard XDS110 information, refer to the XDS110 Debug Probe User’s Guide. Lite XDS110 (MSPM0 LaunchPad Development Kit) The MSPM0 LaunchPad kit include XDS110-ET (Lite) circuit. You can use this debugger to download your firmware into MSPM0 device. shows XDS110-ET circuit. There are two probes in XDS110-ET: 2.54-mm probe: This port supports the SWD protocol and includes a 5-V or 3.3-V power supply. You can connect SWDIO SWCLK 3V3 GND to your board and download firmware into an MSPM0G device. And this probe also supports EnergyTrace technology to measure power consumption precisely in real time. More information for EnergyTrace technology, visit the EnergyTrace Technology tool page. XDS110-ET Circuit 10-pin probe: This port supports the JTAG and SWD protocols and includes a 3.3-V power supply. You can use a 10-pin cable to connect your board and XDS110-ET and download firmware into an MSPM0G device. show the 10-pin cable. Arm Standard 10-Pin Cable Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. The shows the connection between MSPM0G family MCU SWD debug port with the standard JTAG connector. JTAG and MSPM0G Connection For MSPM0G device, you can use XDS110 to implement debug/download function. Here list the contents of the XDS110 and provides instruction on installing the hardware. Standard XDS110 You can purchase a standard XDS110 on ti.com. shows a high-level diagram of the major functional areas and interfaces of the XDS110 probe. XDS110 Probe High-Level Block Diagram More standard XDS110 information, refer to the XDS110 Debug Probe User’s Guide. Lite XDS110 (MSPM0 LaunchPad Development Kit) The MSPM0 LaunchPad kit include XDS110-ET (Lite) circuit. You can use this debugger to download your firmware into MSPM0 device. shows XDS110-ET circuit. There are two probes in XDS110-ET: 2.54-mm probe: This port supports the SWD protocol and includes a 5-V or 3.3-V power supply. You can connect SWDIO SWCLK 3V3 GND to your board and download firmware into an MSPM0G device. And this probe also supports EnergyTrace technology to measure power consumption precisely in real time. More information for EnergyTrace technology, visit the EnergyTrace Technology tool page. XDS110-ET Circuit 10-pin probe: This port supports the JTAG and SWD protocols and includes a 3.3-V power supply. You can use a 10-pin cable to connect your board and XDS110-ET and download firmware into an MSPM0G device. show the 10-pin cable. Arm Standard 10-Pin Cable Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. The shows the connection between MSPM0G family MCU SWD debug port with the standard JTAG connector. JTAG and MSPM0G Connection JTAG and MSPM0G ConnectionFor MSPM0G device, you can use XDS110 to implement debug/download function. Here list the contents of the XDS110 and provides instruction on installing the hardware. Standard XDS110 Standard XDS110You can purchase a standard XDS110 on ti.com. shows a high-level diagram of the major functional areas and interfaces of the XDS110 probe.ti.com XDS110 Probe High-Level Block Diagram XDS110 Probe High-Level Block DiagramMore standard XDS110 information, refer to the XDS110 Debug Probe User’s Guide.XDS110 Debug Probe User’s Guide Lite XDS110 (MSPM0 LaunchPad Development Kit) Lite XDS110 (MSPM0 LaunchPad Development Kit)The MSPM0 LaunchPad kit include XDS110-ET (Lite) circuit. You can use this debugger to download your firmware into MSPM0 device. shows XDS110-ET circuit.There are two probes in XDS110-ET: 2.54-mm probe: This port supports the SWD protocol and includes a 5-V or 3.3-V power supply. You can connect SWDIO SWCLK 3V3 GND to your board and download firmware into an MSPM0G device.2.54-mm probe:And this probe also supports EnergyTrace technology to measure power consumption precisely in real time.More information for EnergyTrace technology, visit the EnergyTrace Technology tool page.EnergyTrace Technology tool page XDS110-ET Circuit XDS110-ET Circuit 10-pin probe: This port supports the JTAG and SWD protocols and includes a 3.3-V power supply. You can use a 10-pin cable to connect your board and XDS110-ET and download firmware into an MSPM0G device. show the 10-pin cable.10-pin probe: Arm Standard 10-Pin Cable Arm Standard 10-Pin Cable Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level. We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability. XDS110-ET 2.54-mm probe does not support JTAG protocol. XDS110-ET 10-pin probe does not support EnergyTrace technology. Standard XDS110 support level shift for debug ports, XDS110-ET just support 3.3v probe level.We do not recommend using the XDS110 to power other devices except the MSPM0G MCU because the XDS110 integrates an LDO with limited current drive capability.XDS110-ET 2.54-mm probe does not support JTAG protocol.XDS110-ET 10-pin probe does not support EnergyTrace technology. Key Analog Peripherals The MSPM0G series MCU includes analog peripheral resources that can provide many analog signal conditioning functions inside the chip. To maximize the use of the MSPM0G's analog peripheral performance, some considerations need to be made in the hardware design. This chapter discusses analog design considerations for many typical analog circuit configurations. ADC Design Considerations MSPM0G devices have a 12-bit, up to 4 Msps, analog-to-digital converter (ADC). The ADC supports fast 12-, 10-, and 8-bit analog-to-digital conversions. The ADC implements a 12-bit SAR core, sample/conversion mode control, and up to 12 independent conversion-and-control buffers. ADC Input Network To achieve the desired conversion speed and keep high accuracy, it is necessary to ensure proper sampling time in hardware design. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. shows a typical ADC model of an MSPM0G MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. It is critical to understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion: tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar) To evaluate continuous high speed (4 Msps) ADC performance, TI recommends adding an external buffer to ensure sufficient signal source drive capability. As a design reference, see the LP-MSPM0G3507 hardware design, which includes a recommended external OPA. OPA Design Considerations The MSPM0G OPA is a zero-drift chopper stabilized operational amplifier with a programmable gain stage. The OPA can used for signal amplification and buffering and can work in general-purpose mode, buffer mode and PGA mode. When using the OPA in general-purpose mode, add an external resistor and capacitor to create the amplifier circuit. But when using buffer mode, it can be configured through software. For PGA mode, software can configure up to 32x PGA gain. The PGA gain is only in the negative terminal. When two or more OPAs are available on a device, the two can be combined to form a differential amplifier. The output equation for the differential amplifier is given by the Vdiff equation in . Two OPA Differential Amplifier Block Diagram and Equation Alternately, when two or more OPAs are available on a device, they can be combined to form a multi-stage or cascaded amplifier. Using the programmable input muxes, all combinations of inverting and non-inverting multi-stage amplifiers can be implemented. The output equation for the noninverting to noninverting cascaded amplifier is given by the Vout equation in . Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation DAC Design Considerations MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength. Not all devices include these two DAC modules. See the device-specific data sheet for details. 8-Bit DAC Block Diagram 8-Bit DAC and OPA Output Block Diagram 12-bit DAC Output Block Diagram COMP Design Considerations The MSPM0G comparator module (COMP) is an analog voltage comparator with general comparator functionality. The COMP module includes internal and external inputs that can be used to flexibly to process analog signals. An internal temperature sensor can be used as a direct input to the COMP. Comparator Diagram The MSPM0G Comparator module also combine two COMP to implement a window comparator function. As shown in , COMP0 and COMP1 can be configured together to create a window comparator. In this configuration, the input signal is connected to the positive terminal of the comparators connected together, and the upper and lower threshold voltages are connected to the negative terminal of the comparators. Window Comparator Mode The COMP module also includes a SHORT switch that can be used to build a simple sample-and-hold for the comparator. As shown in , the required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (R), and the resistance of the external source (RS). The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the below equation. T a u = ( R I + R S ) x C S Depending on the required accuracy, use 3 to 10 Tau as the sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. Comparator Short Switch GPAMP Design Considerations MSPM0G devices includes GPAMP (General Purpose Amplifier) modules that can used for signal amplification with some external resistors and capacitors, as seen in . GPAMP Circuit in Amplify Mode The GPAMP can also be used as a buffer for the internal ADC. shows an example of this configuration. GPAMP Circuit in Buffer Mode Key Analog Peripherals The MSPM0G series MCU includes analog peripheral resources that can provide many analog signal conditioning functions inside the chip. To maximize the use of the MSPM0G's analog peripheral performance, some considerations need to be made in the hardware design. This chapter discusses analog design considerations for many typical analog circuit configurations. The MSPM0G series MCU includes analog peripheral resources that can provide many analog signal conditioning functions inside the chip. To maximize the use of the MSPM0G's analog peripheral performance, some considerations need to be made in the hardware design. This chapter discusses analog design considerations for many typical analog circuit configurations. The MSPM0G series MCU includes analog peripheral resources that can provide many analog signal conditioning functions inside the chip. To maximize the use of the MSPM0G's analog peripheral performance, some considerations need to be made in the hardware design. This chapter discusses analog design considerations for many typical analog circuit configurations. ADC Design Considerations MSPM0G devices have a 12-bit, up to 4 Msps, analog-to-digital converter (ADC). The ADC supports fast 12-, 10-, and 8-bit analog-to-digital conversions. The ADC implements a 12-bit SAR core, sample/conversion mode control, and up to 12 independent conversion-and-control buffers. ADC Input Network To achieve the desired conversion speed and keep high accuracy, it is necessary to ensure proper sampling time in hardware design. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. shows a typical ADC model of an MSPM0G MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. It is critical to understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion: tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar) To evaluate continuous high speed (4 Msps) ADC performance, TI recommends adding an external buffer to ensure sufficient signal source drive capability. As a design reference, see the LP-MSPM0G3507 hardware design, which includes a recommended external OPA. ADC Design Considerations MSPM0G devices have a 12-bit, up to 4 Msps, analog-to-digital converter (ADC). The ADC supports fast 12-, 10-, and 8-bit analog-to-digital conversions. The ADC implements a 12-bit SAR core, sample/conversion mode control, and up to 12 independent conversion-and-control buffers. ADC Input Network To achieve the desired conversion speed and keep high accuracy, it is necessary to ensure proper sampling time in hardware design. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. shows a typical ADC model of an MSPM0G MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. It is critical to understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion: tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar) To evaluate continuous high speed (4 Msps) ADC performance, TI recommends adding an external buffer to ensure sufficient signal source drive capability. As a design reference, see the LP-MSPM0G3507 hardware design, which includes a recommended external OPA. MSPM0G devices have a 12-bit, up to 4 Msps, analog-to-digital converter (ADC). The ADC supports fast 12-, 10-, and 8-bit analog-to-digital conversions. The ADC implements a 12-bit SAR core, sample/conversion mode control, and up to 12 independent conversion-and-control buffers. ADC Input Network To achieve the desired conversion speed and keep high accuracy, it is necessary to ensure proper sampling time in hardware design. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. shows a typical ADC model of an MSPM0G MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. It is critical to understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion: tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar) To evaluate continuous high speed (4 Msps) ADC performance, TI recommends adding an external buffer to ensure sufficient signal source drive capability. As a design reference, see the LP-MSPM0G3507 hardware design, which includes a recommended external OPA. MSPM0G devices have a 12-bit, up to 4 Msps, analog-to-digital converter (ADC). The ADC supports fast 12-, 10-, and 8-bit analog-to-digital conversions. The ADC implements a 12-bit SAR core, sample/conversion mode control, and up to 12 independent conversion-and-control buffers. ADC Input Network ADC Input NetworkTo achieve the desired conversion speed and keep high accuracy, it is necessary to ensure proper sampling time in hardware design. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. shows a typical ADC model of an MSPM0G MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. It is critical to understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion:tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar)sampleparinn+2S/H1ParTo evaluate continuous high speed (4 Msps) ADC performance, TI recommends adding an external buffer to ensure sufficient signal source drive capability. As a design reference, see the LP-MSPM0G3507 hardware design, which includes a recommended external OPA. OPA Design Considerations The MSPM0G OPA is a zero-drift chopper stabilized operational amplifier with a programmable gain stage. The OPA can used for signal amplification and buffering and can work in general-purpose mode, buffer mode and PGA mode. When using the OPA in general-purpose mode, add an external resistor and capacitor to create the amplifier circuit. But when using buffer mode, it can be configured through software. For PGA mode, software can configure up to 32x PGA gain. The PGA gain is only in the negative terminal. When two or more OPAs are available on a device, the two can be combined to form a differential amplifier. The output equation for the differential amplifier is given by the Vdiff equation in . Two OPA Differential Amplifier Block Diagram and Equation Alternately, when two or more OPAs are available on a device, they can be combined to form a multi-stage or cascaded amplifier. Using the programmable input muxes, all combinations of inverting and non-inverting multi-stage amplifiers can be implemented. The output equation for the noninverting to noninverting cascaded amplifier is given by the Vout equation in . Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation OPA Design Considerations The MSPM0G OPA is a zero-drift chopper stabilized operational amplifier with a programmable gain stage. The OPA can used for signal amplification and buffering and can work in general-purpose mode, buffer mode and PGA mode. When using the OPA in general-purpose mode, add an external resistor and capacitor to create the amplifier circuit. But when using buffer mode, it can be configured through software. For PGA mode, software can configure up to 32x PGA gain. The PGA gain is only in the negative terminal. When two or more OPAs are available on a device, the two can be combined to form a differential amplifier. The output equation for the differential amplifier is given by the Vdiff equation in . Two OPA Differential Amplifier Block Diagram and Equation Alternately, when two or more OPAs are available on a device, they can be combined to form a multi-stage or cascaded amplifier. Using the programmable input muxes, all combinations of inverting and non-inverting multi-stage amplifiers can be implemented. The output equation for the noninverting to noninverting cascaded amplifier is given by the Vout equation in . Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation The MSPM0G OPA is a zero-drift chopper stabilized operational amplifier with a programmable gain stage. The OPA can used for signal amplification and buffering and can work in general-purpose mode, buffer mode and PGA mode. When using the OPA in general-purpose mode, add an external resistor and capacitor to create the amplifier circuit. But when using buffer mode, it can be configured through software. For PGA mode, software can configure up to 32x PGA gain. The PGA gain is only in the negative terminal. When two or more OPAs are available on a device, the two can be combined to form a differential amplifier. The output equation for the differential amplifier is given by the Vdiff equation in . Two OPA Differential Amplifier Block Diagram and Equation Alternately, when two or more OPAs are available on a device, they can be combined to form a multi-stage or cascaded amplifier. Using the programmable input muxes, all combinations of inverting and non-inverting multi-stage amplifiers can be implemented. The output equation for the noninverting to noninverting cascaded amplifier is given by the Vout equation in . Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation The MSPM0G OPA is a zero-drift chopper stabilized operational amplifier with a programmable gain stage. The OPA can used for signal amplification and buffering and can work in general-purpose mode, buffer mode and PGA mode.When using the OPA in general-purpose mode, add an external resistor and capacitor to create the amplifier circuit. But when using buffer mode, it can be configured through software. For PGA mode, software can configure up to 32x PGA gain.The PGA gain is only in the negative terminal.When two or more OPAs are available on a device, the two can be combined to form a differential amplifier. The output equation for the differential amplifier is given by the Vdiff equation in .diff Two OPA Differential Amplifier Block Diagram and Equation Two OPA Differential Amplifier Block Diagram and EquationAlternately, when two or more OPAs are available on a device, they can be combined to form a multi-stage or cascaded amplifier. Using the programmable input muxes, all combinations of inverting and non-inverting multi-stage amplifiers can be implemented. The output equation for the noninverting to noninverting cascaded amplifier is given by the Vout equation in .out Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation Two OPA Noninverting to Noninverting Cascade Amplifier Block Diagram and Equation DAC Design Considerations MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength. Not all devices include these two DAC modules. See the device-specific data sheet for details. 8-Bit DAC Block Diagram 8-Bit DAC and OPA Output Block Diagram 12-bit DAC Output Block Diagram DAC Design Considerations MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength. Not all devices include these two DAC modules. See the device-specific data sheet for details. 8-Bit DAC Block Diagram 8-Bit DAC and OPA Output Block Diagram 12-bit DAC Output Block Diagram MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength. Not all devices include these two DAC modules. See the device-specific data sheet for details. 8-Bit DAC Block Diagram 8-Bit DAC and OPA Output Block Diagram 12-bit DAC Output Block Diagram MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength. MSPM0G devices include two DAC modules: 8-bit and 12-bit. The DAC can be used as the reference voltage and also can work with the OPA to drive the output pad directly. 12-bit DAC modules include a buffer, thus this can output to pad directly. However, the 8-bit DAC module is normally used as internal reference voltage for OPA and COMP, therefore to output to an external pin, the OPA must be configured into buffer mode to improve the drive strength.Not all devices include these two DAC modules. See the device-specific data sheet for details. 8-Bit DAC Block Diagram 8-Bit DAC Block Diagram 8-Bit DAC and OPA Output Block Diagram 8-Bit DAC and OPA Output Block Diagram 12-bit DAC Output Block Diagram 12-bit DAC Output Block Diagram COMP Design Considerations The MSPM0G comparator module (COMP) is an analog voltage comparator with general comparator functionality. The COMP module includes internal and external inputs that can be used to flexibly to process analog signals. An internal temperature sensor can be used as a direct input to the COMP. Comparator Diagram The MSPM0G Comparator module also combine two COMP to implement a window comparator function. As shown in , COMP0 and COMP1 can be configured together to create a window comparator. In this configuration, the input signal is connected to the positive terminal of the comparators connected together, and the upper and lower threshold voltages are connected to the negative terminal of the comparators. Window Comparator Mode The COMP module also includes a SHORT switch that can be used to build a simple sample-and-hold for the comparator. As shown in , the required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (R), and the resistance of the external source (RS). The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the below equation. T a u = ( R I + R S ) x C S Depending on the required accuracy, use 3 to 10 Tau as the sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. Comparator Short Switch COMP Design Considerations The MSPM0G comparator module (COMP) is an analog voltage comparator with general comparator functionality. The COMP module includes internal and external inputs that can be used to flexibly to process analog signals. An internal temperature sensor can be used as a direct input to the COMP. Comparator Diagram The MSPM0G Comparator module also combine two COMP to implement a window comparator function. As shown in , COMP0 and COMP1 can be configured together to create a window comparator. In this configuration, the input signal is connected to the positive terminal of the comparators connected together, and the upper and lower threshold voltages are connected to the negative terminal of the comparators. Window Comparator Mode The COMP module also includes a SHORT switch that can be used to build a simple sample-and-hold for the comparator. As shown in , the required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (R), and the resistance of the external source (RS). The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the below equation. T a u = ( R I + R S ) x C S Depending on the required accuracy, use 3 to 10 Tau as the sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. Comparator Short Switch The MSPM0G comparator module (COMP) is an analog voltage comparator with general comparator functionality. The COMP module includes internal and external inputs that can be used to flexibly to process analog signals. An internal temperature sensor can be used as a direct input to the COMP. Comparator Diagram The MSPM0G Comparator module also combine two COMP to implement a window comparator function. As shown in , COMP0 and COMP1 can be configured together to create a window comparator. In this configuration, the input signal is connected to the positive terminal of the comparators connected together, and the upper and lower threshold voltages are connected to the negative terminal of the comparators. Window Comparator Mode The COMP module also includes a SHORT switch that can be used to build a simple sample-and-hold for the comparator. As shown in , the required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (R), and the resistance of the external source (RS). The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the below equation. T a u = ( R I + R S ) x C S Depending on the required accuracy, use 3 to 10 Tau as the sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. Comparator Short Switch The MSPM0G comparator module (COMP) is an analog voltage comparator with general comparator functionality.The COMP module includes internal and external inputs that can be used to flexibly to process analog signals. An internal temperature sensor can be used as a direct input to the COMP. Comparator Diagram Comparator DiagramThe MSPM0G Comparator module also combine two COMP to implement a window comparator function. As shown in , COMP0 and COMP1 can be configured together to create a window comparator. In this configuration, the input signal is connected to the positive terminal of the comparators connected together, and the upper and lower threshold voltages are connected to the negative terminal of the comparators. Window Comparator Mode Window Comparator ModeThe COMP module also includes a SHORT switch that can be used to build a simple sample-and-hold for the comparator.As shown in , the required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (R), and the resistance of the external source (RS). The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the below equation. T a u = ( R I + R S ) x C S T a u = ( R I + R S ) x C S T a u = ( R I + R S ) x C S T a u T a u au= ( ( R I R I I+ R S R S S ) ) x C S C S SDepending on the required accuracy, use 3 to 10 Tau as the sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. Comparator Short Switch Comparator Short Switch GPAMP Design Considerations MSPM0G devices includes GPAMP (General Purpose Amplifier) modules that can used for signal amplification with some external resistors and capacitors, as seen in . GPAMP Circuit in Amplify Mode The GPAMP can also be used as a buffer for the internal ADC. shows an example of this configuration. GPAMP Circuit in Buffer Mode GPAMP Design Considerations MSPM0G devices includes GPAMP (General Purpose Amplifier) modules that can used for signal amplification with some external resistors and capacitors, as seen in . GPAMP Circuit in Amplify Mode The GPAMP can also be used as a buffer for the internal ADC. shows an example of this configuration. GPAMP Circuit in Buffer Mode MSPM0G devices includes GPAMP (General Purpose Amplifier) modules that can used for signal amplification with some external resistors and capacitors, as seen in . GPAMP Circuit in Amplify Mode The GPAMP can also be used as a buffer for the internal ADC. shows an example of this configuration. GPAMP Circuit in Buffer Mode MSPM0G devices includes GPAMP (General Purpose Amplifier) modules that can used for signal amplification with some external resistors and capacitors, as seen in . GPAMP Circuit in Amplify Mode GPAMP Circuit in Amplify ModeThe GPAMP can also be used as a buffer for the internal ADC. shows an example of this configuration. GPAMP Circuit in Buffer Mode GPAMP Circuit in Buffer Mode Key Digital Peripherals The MSPM0G series MCU includes a wealth of digital peripheral resources, like Timer, UART, SPI, MCAN, LIN etc. which provide rich communication capabilities. To maximize the use of the MSPM0G's digital peripherals, some considerations need to be made in the hardware design. This chapter discusses design considerations for many typical digital peripheral configurations. Timer Resources and Design Considerations Timers are one of the most basic and important modules in any MCU, and this resource is used in all applications. It can be used to process tasks regularly, delay, output PWM waveforms to drive o devices, detect the width and frequency of external pulses, simulate waveform outputs, and more. The MSPM0G series MCU includes three types of Timer module: TIMA, TIMG and TIMH. The advanced timer (TIMA), general-purpose timer (TIMG) and high-resolution timer (TIMH) are all timer counting modules that can be used for a variety of functions, including measuring the input signal edge and period (capture mode) or generating output waveforms (compare mode output) like PWM signals. However, TIMA adds additional features such as complementary PWM with dead band insertion, and TIMH has a 24-bit resolution counter. A summary of the different features and configurations of each timer is shown in the following tables. TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - UART and LIN Resources and Design Considerations The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in , UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function. UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications. MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness. The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. shows a typical interface implemented using the TI TLIN1021A LIN transceiver. Typical LIN TLIN1021A Transceiver Only a single wire is required for communication and is commonly included in the vehicle wiring harness. and show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet. Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Responder) With MSPM0G MCAN Design Considerations Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may coexist on the same network without any conflict provided that partial network transceivers, which can detect and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is compliant to ISO 11898-1:2015. Some MSPM0G devices include MCAN and LIN modules. To connect to CAN and LIN buses normally, the device needs an external MCAN transceiver or LIN transceiver as shown in . MCAN Typical Bus Wiring TCAN1042GV is a CAN transceiver and meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. It can be used in CAN FD networks up to 5 Mbps (megabits per second) with the secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This device has a low-power standby mode with remote wake request feature. Additionally, this device includes many protection features to enhance device and network robustness. includes a reference design circuit. For more details, refer to the TCAN1042 data sheet. Typical CAN Bus Application With MSPM0G I2C and SPI Design Considerations SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow to design a system based on your requirements. Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it. External Connections for Different SPI Configurations For I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the . External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device. MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us Typical I2C Bus Connection Key Digital Peripherals The MSPM0G series MCU includes a wealth of digital peripheral resources, like Timer, UART, SPI, MCAN, LIN etc. which provide rich communication capabilities. To maximize the use of the MSPM0G's digital peripherals, some considerations need to be made in the hardware design. This chapter discusses design considerations for many typical digital peripheral configurations. The MSPM0G series MCU includes a wealth of digital peripheral resources, like Timer, UART, SPI, MCAN, LIN etc. which provide rich communication capabilities. To maximize the use of the MSPM0G's digital peripherals, some considerations need to be made in the hardware design. This chapter discusses design considerations for many typical digital peripheral configurations. Timer Resources and Design Considerations Timers are one of the most basic and important modules in any MCU, and this resource is used in all applications. It can be used to process tasks regularly, delay, output PWM waveforms to drive o devices, detect the width and frequency of external pulses, simulate waveform outputs, and more. The MSPM0G series MCU includes three types of Timer module: TIMA, TIMG and TIMH. The advanced timer (TIMA), general-purpose timer (TIMG) and high-resolution timer (TIMH) are all timer counting modules that can be used for a variety of functions, including measuring the input signal edge and period (capture mode) or generating output waveforms (compare mode output) like PWM signals. However, TIMA adds additional features such as complementary PWM with dead band insertion, and TIMH has a 24-bit resolution counter. A summary of the different features and configurations of each timer is shown in the following tables. TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - Timer Resources and Design Considerations Timers are one of the most basic and important modules in any MCU, and this resource is used in all applications. It can be used to process tasks regularly, delay, output PWM waveforms to drive o devices, detect the width and frequency of external pulses, simulate waveform outputs, and more. The MSPM0G series MCU includes three types of Timer module: TIMA, TIMG and TIMH. The advanced timer (TIMA), general-purpose timer (TIMG) and high-resolution timer (TIMH) are all timer counting modules that can be used for a variety of functions, including measuring the input signal edge and period (capture mode) or generating output waveforms (compare mode output) like PWM signals. However, TIMA adds additional features such as complementary PWM with dead band insertion, and TIMH has a 24-bit resolution counter. A summary of the different features and configurations of each timer is shown in the following tables. TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - Timers are one of the most basic and important modules in any MCU, and this resource is used in all applications. It can be used to process tasks regularly, delay, output PWM waveforms to drive o devices, detect the width and frequency of external pulses, simulate waveform outputs, and more. The MSPM0G series MCU includes three types of Timer module: TIMA, TIMG and TIMH. The advanced timer (TIMA), general-purpose timer (TIMG) and high-resolution timer (TIMH) are all timer counting modules that can be used for a variety of functions, including measuring the input signal edge and period (capture mode) or generating output waveforms (compare mode output) like PWM signals. However, TIMA adds additional features such as complementary PWM with dead band insertion, and TIMH has a 24-bit resolution counter. A summary of the different features and configurations of each timer is shown in the following tables. TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - Timers are one of the most basic and important modules in any MCU, and this resource is used in all applications. It can be used to process tasks regularly, delay, output PWM waveforms to drive o devices, detect the width and frequency of external pulses, simulate waveform outputs, and more.The MSPM0G series MCU includes three types of Timer module: TIMA, TIMG and TIMH. The advanced timer (TIMA), general-purpose timer (TIMG) and high-resolution timer (TIMH) are all timer counting modules that can be used for a variety of functions, including measuring the input signal edge and period (capture mode) or generating output waveforms (compare mode output) like PWM signals. However, TIMA adds additional features such as complementary PWM with dead band insertion, and TIMH has a 24-bit resolution counter. A summary of the different features and configurations of each timer is shown in the following tables. TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI InstancePower DomainCounter ResolutionPrescalerRepeat CounterCCP ChannelsPhase LoadShadow LoadPipelined CCDead bandFault HandlerQEI TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes - TIMA0PD116-bit8-bit8-bit4YesYesYesYesYes- TIMA1 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA1PD116-bit8-bit-2YesYesYesYesYes- TIMA2 PD1 16-bit 8-bit - 2 Yes Yes Yes Yes Yes - TIMA2PD116-bit8-bit-2YesYesYesYesYes- TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI InstancePower DomainCounter ResolutionPrescalerRepeat CounterCCP ChannelsPhase LoadShadow LoadPipelined CCDead bandFault HandlerQEI TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG0 PD0 16-bit 8-bit - 2 - - - - - - TIMG0PD016-bit8-bit-2------ TIMG1 PD0 16-bit 8-bit - 2 - - - - - - TIMG1PD016-bit8-bit-2------ TIMG2 PD0 16-bit 8-bit - 2 - - - - - - TIMG2PD016-bit8-bit-2------ TIMG3 PD0 16-bit 8-bit - 2 - - - - - - TIMG3PD016-bit8-bit-2------ TIMG4 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG4PD016-bit8-bit-2-YesYes--- TIMG5 PD0 16-bit 8-bit - 2 - Yes Yes - - - TIMG5PD016-bit8-bit-2-YesYes--- TIMG6 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG6PD116-bit8-bit-2-YesYes--- TIMG7 PD1 16-bit 8-bit - 2 - Yes Yes - - - TIMG7PD116-bit8-bit-2-YesYes--- TIMG8 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG8PD016-bit8-bit-2-----Yes TIMG9 PD0 16-bit 8-bit - 2 - - - - - Yes TIMG9PD016-bit8-bit-2-----Yes TIMG10 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG10PD116-bit8-bit-2-----Yes TIMG11 PD1 16-bit 8-bit - 2 - - - - - Yes TIMG11PD116-bit8-bit-2-----Yes First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual First look at the device specific data sheet to check which TIMG instances are available on the device Need to check what features are available for each TIMG instance in Technical Reference Manual TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - TIMH Instance Configuration Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI Instance Power Domain Counter Resolution Prescaler Repeat Counter CCP Channels Phase Load Shadow Load Pipelined CC Dead band Fault Handler QEI InstancePower DomainCounter ResolutionPrescalerRepeat CounterCCP ChannelsPhase LoadShadow LoadPipelined CCDead bandFault HandlerQEI TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH1 PD1 24-bit - - 2 - - Yes - - - TIMH0 PD1 24-bit - - 2 - - Yes - - - TIMH0PD124-bit--2--Yes--- TIMH1 PD1 24-bit - - 2 - - Yes - - - TIMH1PD124-bit--2--Yes--- UART and LIN Resources and Design Considerations The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in , UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function. UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications. MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness. The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. shows a typical interface implemented using the TI TLIN1021A LIN transceiver. Typical LIN TLIN1021A Transceiver Only a single wire is required for communication and is commonly included in the vehicle wiring harness. and show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet. Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Responder) With MSPM0G UART and LIN Resources and Design Considerations The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in , UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function. UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications. MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness. The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. shows a typical interface implemented using the TI TLIN1021A LIN transceiver. Typical LIN TLIN1021A Transceiver Only a single wire is required for communication and is commonly included in the vehicle wiring harness. and show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet. Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Responder) With MSPM0G The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in , UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function. UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications. MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness. The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. shows a typical interface implemented using the TI TLIN1021A LIN transceiver. Typical LIN TLIN1021A Transceiver Only a single wire is required for communication and is commonly included in the vehicle wiring harness. and show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet. Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Responder) With MSPM0G The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in , UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function. UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - UART Features UART0 (Extend) UART1 (Main) UART Features UART0 (Extend) UART1 (Main) UART FeaturesUART0 (Extend)UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - Active in Stop and Standby Mode Yes Yes Active in Stop and Standby ModeYesYes Separate transmit and receive FIFOs Yes Yes Separate transmit and receive FIFOsYesYes Support hardware flow control Yes Yes Support hardware flow controlYesYes Support 9-bit configuration Yes Yes Support 9-bit configurationYesYes Support LIN mode Yes - Support LIN modeYes- Support DALI Yes - Support DALIYes- Support IrDA Yes - Support IrDAYes- Support ISO7816 Smart Card Yes - Support ISO7816 Smart CardYes- Support Manchester coding Yes - Support Manchester codingYes-The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications. MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns MSPM0G UART Specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERSTEST CONDITIONSMINTYPMAXUNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns AGFSELx = 1 8 15 55 ns AGFSELx = 2 18 38 115 ns AGFSELx = 3 30 74 165 ns fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UARTUART input clock frequencyUART in Power Domain180MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fUART UARTUART input clock frequencyUART in Power Domain040MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLKBITCLK clock frequency(equals baud rate in MBaud)UART in Power Domain110MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz fBITCLK BITCLKBITCLK clock frequency(equals baud rate in MBaud)5MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns tSP SPPulse duration of spikes suppressed by input filterAGFSELx = 055.532ns AGFSELx = 1 8 15 55 ns AGFSELx = 181555ns AGFSELx = 2 18 38 115 ns AGFSELx = 21838115ns AGFSELx = 3 30 74 165 ns AGFSELx = 33074165nsLocal Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness.The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. shows a typical interface implemented using the TI TLIN1021A LIN transceiver. Typical LIN TLIN1021A Transceiver Typical LIN TLIN1021A TransceiverOnly a single wire is required for communication and is commonly included in the vehicle wiring harness. and show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet. Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Commander) With MSPM0G Typical LIN Application (Responder) With MSPM0G Typical LIN Application (Responder) With MSPM0G MCAN Design Considerations Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may coexist on the same network without any conflict provided that partial network transceivers, which can detect and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is compliant to ISO 11898-1:2015. Some MSPM0G devices include MCAN and LIN modules. To connect to CAN and LIN buses normally, the device needs an external MCAN transceiver or LIN transceiver as shown in . MCAN Typical Bus Wiring TCAN1042GV is a CAN transceiver and meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. It can be used in CAN FD networks up to 5 Mbps (megabits per second) with the secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This device has a low-power standby mode with remote wake request feature. Additionally, this device includes many protection features to enhance device and network robustness. includes a reference design circuit. For more details, refer to the TCAN1042 data sheet. Typical CAN Bus Application With MSPM0G MCAN Design Considerations Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may coexist on the same network without any conflict provided that partial network transceivers, which can detect and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is compliant to ISO 11898-1:2015. Some MSPM0G devices include MCAN and LIN modules. To connect to CAN and LIN buses normally, the device needs an external MCAN transceiver or LIN transceiver as shown in . MCAN Typical Bus Wiring TCAN1042GV is a CAN transceiver and meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. It can be used in CAN FD networks up to 5 Mbps (megabits per second) with the secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This device has a low-power standby mode with remote wake request feature. Additionally, this device includes many protection features to enhance device and network robustness. includes a reference design circuit. For more details, refer to the TCAN1042 data sheet. Typical CAN Bus Application With MSPM0G Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may coexist on the same network without any conflict provided that partial network transceivers, which can detect and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is compliant to ISO 11898-1:2015. Some MSPM0G devices include MCAN and LIN modules. To connect to CAN and LIN buses normally, the device needs an external MCAN transceiver or LIN transceiver as shown in . MCAN Typical Bus Wiring TCAN1042GV is a CAN transceiver and meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. It can be used in CAN FD networks up to 5 Mbps (megabits per second) with the secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This device has a low-power standby mode with remote wake request feature. Additionally, this device includes many protection features to enhance device and network robustness. includes a reference design circuit. For more details, refer to the TCAN1042 data sheet. Typical CAN Bus Application With MSPM0G Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides data consistency in every node of the system.The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may coexist on the same network without any conflict provided that partial network transceivers, which can detect and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is compliant to ISO 11898-1:2015. Some MSPM0G devices include MCAN and LIN modules. To connect to CAN and LIN buses normally, the device needs an external MCAN transceiver or LIN transceiver as shown in . MCAN Typical Bus Wiring MCAN Typical Bus WiringTCAN1042GV is a CAN transceiver and meets the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. It can be used in CAN FD networks up to 5 Mbps (megabits per second) with the secondary power supply input for I/O level shifting the input pin thresholds and RXD output level. This device has a low-power standby mode with remote wake request feature. Additionally, this device includes many protection features to enhance device and network robustness. includes a reference design circuit. For more details, refer to the TCAN1042 data sheet. Typical CAN Bus Application With MSPM0G Typical CAN Bus Application With MSPM0G I2C and SPI Design Considerations SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow to design a system based on your requirements. Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it. External Connections for Different SPI Configurations For I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the . External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device. MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us Typical I2C Bus Connection I2C and SPI Design Considerations SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow to design a system based on your requirements. Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it. External Connections for Different SPI Configurations For I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the . External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device. MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us Typical I2C Bus Connection SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow to design a system based on your requirements. Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it. External Connections for Different SPI Configurations For I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the . External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device. MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us Typical I2C Bus Connection SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow to design a system based on your requirements.Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it. External Connections for Different SPI Configurations External Connections for Different SPI ConfigurationsFor I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the .External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device.GPIOs MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us MSPM0G I2C Characteristics PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT PARAMETERSTEST CONDITIONSStandard modeFast modeFast mode plusUNIT MIN MAX MIN MAX MIN MAX MINMAXMINMAXMINMAX fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fSCL SCL clock frequency 100K 400K 1M MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 us tSU,DAT Data setup time 250 100 50 us tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz fI2C I2CI2C input clock frequencyI2C in Power Domain0404040MHz fSCL SCL clock frequency 100K 400K 1M MHz fSCL SCLSCL clock frequency100K400K1MMHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tHD,STA HD,STAHold time (repeated) START40.60.26us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tLOW LOWLOW period of the SCL clock4.71.30.5us tHIGH High period of the SCL clock 4 0.6 0.26 us tHIGH HIGHHigh period of the SCL clock40.60.26us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tSU,STA SU,STASetup time for a repeated START4.70.60.26us tHD,DAT Data hold time 0 0 0 us tHD,DAT HD,DATData hold time000us tSU,DAT Data setup time 250 100 50 us tSU,DAT SU,DATData setup time25010050us tSU,STO Setup time for STOP 4 0.6 0.26 us tSU,STO SU,STOSetup time for STOP40.60.26us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tBUF BUFBus free time between a STOP and START condition4.71.30.5us tVD;DAT Data valid time 3.46 0.9 0.45 us tVD;DAT VD;DATData valid time3.460.90.45us tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us tVD;ACK VD;ACKData valid acknowledge time3.460.90.45us Typical I2C Bus Connection Typical I2C Bus Connection GPIOs MSPM0G series MCUs include standard-drive I/O (SDIO), high-drive I/O (HDIO), high-speed I/O (HSIO), and 5-V-tolerant open-drain I/O (ODIO). Users can flexibly choose the appropriate I/O type based on actual requirements. The following characteristics need to be considered in hardware design. GPIO Output Switching Speed and Load Capacitance When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device’s data sheet. #GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0G device. MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. GPIO Current Sink and Source MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. SDIO and HSIO are able to sink or source a maximum current of 6 mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20 mA (typical)). However, the total combined current must be less than IVDD (80 mA typical). High-Speed GPIOs (HSIO) HSIO can support up to 40MHz frequency, and this speed is related to bus clock, supply voltage, and load capacitance. Users can also select the output max frequency via the DRV bit in the DIO register. High-Drive GPIOs (HDIO) HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in , TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see ). Suggested ODIO Circuit Communicate With a 1.8-V Device Without a Level Shifter The MSPM0G series devices use a 3.3-V logic level (excluding ODIO). If you need to communicate with 1.8-V devices and do not use external level shifter devices, shows a suggested circuit for interfacing with a 1.8-V device. Suggested Communication Circuit With 1.8-V Device Two MOSFET are used in this circuit - check the VGS to ensure this MOSFET can fully turn on with a low RDS(on): for 1.8-V device, use less than 1.8-V VGS MOSFET. However, too low VGS MOSFET, can cause the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error. U1 output and U2 input U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4. U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 input and U2 output U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”. U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". Unused Pins Connection All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free or floating; for example, I/Os should be set to 0 or 1 (pullup or pulldown enabled on the unused I/O pins) and unused features should be disabled. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. GPIOs MSPM0G series MCUs include standard-drive I/O (SDIO), high-drive I/O (HDIO), high-speed I/O (HSIO), and 5-V-tolerant open-drain I/O (ODIO). Users can flexibly choose the appropriate I/O type based on actual requirements. The following characteristics need to be considered in hardware design. MSPM0G series MCUs include standard-drive I/O (SDIO), high-drive I/O (HDIO), high-speed I/O (HSIO), and 5-V-tolerant open-drain I/O (ODIO). Users can flexibly choose the appropriate I/O type based on actual requirements. The following characteristics need to be considered in hardware design. GPIO Output Switching Speed and Load Capacitance When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device’s data sheet. #GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0G device. MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. GPIO Output Switching Speed and Load Capacitance When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device’s data sheet. #GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0G device. MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device’s data sheet. #GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0G device. MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. When using the GPIO as I/O, design considerations must be made to ensure correct operation. As load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes pin parasitic capacitance (Ci = 5pF (Typical)) and the effects of the board traces. I/O characteristics are available in the device’s data sheet. #GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 list the I/O output frequency characteristics of the MSPM0G device.#GUID-C11ED55B-848F-46FA-BC6E-2164075F7D9A/GUID-2DB7FB01-4546-4826-AC28-667DFDBA74D7 MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns MSPM0G GPIO Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz VDD ≥ 2.7 V, CL = 20 pF 32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns fmax Port output frequency SDIO VDD ≥ 1.71 V, CL = 20 pF 16 MHz fmax maxPort output frequencySDIO VDD ≥ 1.71 V, CL = 20 pFL16MHz VDD ≥ 2.7 V, CL = 20 pF 32 VDD ≥ 2.7 V, CL = 20 pFL32 HSIO VDD ≥ 1.71 V, DRV = 0, CL = 20 pF 16 HSIOVDD ≥ 1.71 V, DRV = 0, CL = 20 pFL16 VDD ≥ 1.71 V, DRV = 1, CL = 20 pF 24 VDD ≥ 1.71 V, DRV = 1, CL = 20 pFL24 VDD ≥ 2.7 V, DRV = 0, CL = 20 pF 32 VDD ≥ 2.7 V, DRV = 0, CL = 20 pFL32 VDD ≥ 2.7 V, DRV = 1, CL = 20 pF 40 VDD ≥ 2.7 V, DRV = 1, CL = 20 pFL40 ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 1 ODIOVDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF+L1 tr,tf Output rise or fall time All output ports except ODIO VDD ≥ 1.71 V 0.3*fmax s tr,tf rfOutput rise or fall timeAll output ports except ODIOVDD ≥ 1.71 V0.3*fmax maxs tf Output fall time ODIO VDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF 20*VDD/5.5 120 ns tf fOutput fall timeODIOVDD ≥ 1.71 V, FM+, CL = 20 pF to 100 pF+L20*VDD/5.5120ns The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency. The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. The output voltage reaches at least 10% and 90% Vcc at the specified toggle frequency.The output rise time of open-drain I/Os is determined by pullup resistance and load capacitance. GPIO Current Sink and Source MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. SDIO and HSIO are able to sink or source a maximum current of 6 mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20 mA (typical)). However, the total combined current must be less than IVDD (80 mA typical). GPIO Current Sink and Source MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. SDIO and HSIO are able to sink or source a maximum current of 6 mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20 mA (typical)). However, the total combined current must be less than IVDD (80 mA typical). MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. SDIO and HSIO are able to sink or source a maximum current of 6 mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20 mA (typical)). However, the total combined current must be less than IVDD (80 mA typical). MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz MSPM0G GPIO Absolute Maximum Ratings MSPM0G GPIO Absolute Maximum Ratings MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin 1.35 V CVDD Capacitor placed between VDD and VSS 10 uF CVCORE Capacitor placed between VCORE and VSS 470 nF TA Ambient temperature, T version –40 105 °C Ambient temperature, S version –40 125 TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, T version 125 °C TJ Max junction temperature, S and Q versions 130 °C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz VDD Supply voltage 1.62 3.6 V VDDSupply voltage1.623.6V VCORE Voltage on VCORE pin 1.35 V VCOREVoltage on VCORE pin 1.35V CVDD Capacitor placed between VDD and VSS 10 uF CVDD VDDCapacitor placed between VDD and VSS 10uF CVCORE Capacitor placed between VCORE and VSS 470 nF CVCORE VCORECapacitor placed between VCORE and VSS 470nF TA Ambient temperature, T version –40 105 °C TA AAmbient temperature, T version–40105°C Ambient temperature, S version –40 125 Ambient temperature, S version–40125 TA Ambient temperature, Q version -40 125 °C TA AAmbient temperature, Q version-40125°C TJ Max junction temperature, T version 125 °C TJ JMax junction temperature, T version125°C TJ Max junction temperature, S and Q versions 130 °C TJ JMax junction temperature, S and Q versions130°C fMCLK(PD1 bus clock) MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80 MHz fMCLK(PD1 bus clock) MCLK(PD1 bus clock)MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24 fULPCLK(PD0 bus clock) ULPCLK frequency 40 MHz fULPCLK(PD0 bus clock) ULPCLK(PD0 bus clock)ULPCLK frequency40MHz The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. The total current of I/O must be less than the maximum value of IVDD. HDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet. The total current of I/O must be less than the maximum value of IVDD.VDDHDIO, HSIO and ODIO are patched in a fixed pin, see to the device data sheet.SDIO and HSIO are able to sink or source a maximum current of 6 mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20 mA (typical)). However, the total combined current must be less than IVDD (80 mA typical). High-Speed GPIOs (HSIO) HSIO can support up to 40MHz frequency, and this speed is related to bus clock, supply voltage, and load capacitance. Users can also select the output max frequency via the DRV bit in the DIO register. High-Speed GPIOs (HSIO) HSIO can support up to 40MHz frequency, and this speed is related to bus clock, supply voltage, and load capacitance. Users can also select the output max frequency via the DRV bit in the DIO register. HSIO can support up to 40MHz frequency, and this speed is related to bus clock, supply voltage, and load capacitance. Users can also select the output max frequency via the DRV bit in the DIO register. HSIO can support up to 40MHz frequency, and this speed is related to bus clock, supply voltage, and load capacitance. Users can also select the output max frequency via the DRV bit in the DIO register. High-Drive GPIOs (HDIO) HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. High-Drive GPIOs (HDIO) HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. HDIO are able to output 20mA current to drive a load, and the max source current is related to supply voltage. Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in , TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see ). Suggested ODIO Circuit Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in , TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see ). Suggested ODIO Circuit ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in , TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see ). Suggested ODIO Circuit ODIO are tolerant to 5-V input. Because the ODIO are open drain, an external pullup resistor is required for the pin to be able to output high. This I/O can used for UART or I2C interfaces with different voltage levels. To limit the current, place a series resistor between the pin and the pullup resistor, and the RSERIES should be no less than 250 Ω. As shown in , TI recommends 270 Ω. The value of the pullup resistor depends on the output frequency (see ).SERIES Suggested ODIO Circuit Suggested ODIO Circuit Communicate With a 1.8-V Device Without a Level Shifter The MSPM0G series devices use a 3.3-V logic level (excluding ODIO). If you need to communicate with 1.8-V devices and do not use external level shifter devices, shows a suggested circuit for interfacing with a 1.8-V device. Suggested Communication Circuit With 1.8-V Device Two MOSFET are used in this circuit - check the VGS to ensure this MOSFET can fully turn on with a low RDS(on): for 1.8-V device, use less than 1.8-V VGS MOSFET. However, too low VGS MOSFET, can cause the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error. U1 output and U2 input U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4. U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 input and U2 output U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”. U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". Communicate With a 1.8-V Device Without a Level Shifter The MSPM0G series devices use a 3.3-V logic level (excluding ODIO). If you need to communicate with 1.8-V devices and do not use external level shifter devices, shows a suggested circuit for interfacing with a 1.8-V device. Suggested Communication Circuit With 1.8-V Device Two MOSFET are used in this circuit - check the VGS to ensure this MOSFET can fully turn on with a low RDS(on): for 1.8-V device, use less than 1.8-V VGS MOSFET. However, too low VGS MOSFET, can cause the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error. U1 output and U2 input U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4. U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 input and U2 output U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”. U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". The MSPM0G series devices use a 3.3-V logic level (excluding ODIO). If you need to communicate with 1.8-V devices and do not use external level shifter devices, shows a suggested circuit for interfacing with a 1.8-V device. Suggested Communication Circuit With 1.8-V Device Two MOSFET are used in this circuit - check the VGS to ensure this MOSFET can fully turn on with a low RDS(on): for 1.8-V device, use less than 1.8-V VGS MOSFET. However, too low VGS MOSFET, can cause the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error. The MSPM0G series devices use a 3.3-V logic level (excluding ODIO). If you need to communicate with 1.8-V devices and do not use external level shifter devices, shows a suggested circuit for interfacing with a 1.8-V device. Suggested Communication Circuit With 1.8-V Device Suggested Communication Circuit With 1.8-V DeviceTwo MOSFET are used in this circuit - check the VGS to ensure this MOSFET can fully turn on with a low RDS(on): for 1.8-V device, use less than 1.8-V VGS MOSFET. However, too low VGS MOSFET, can cause the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error. U1 output and U2 input U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4. U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 output and U2 input U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4. U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 output “1.8v high”, Q1 VGS around 0, thus Q1 turn off, U2 reads “3.3v high” with R4.U1 output “low”, Q1 VGS around 1.8v, thus Q1 turn on, U2 reads “low”. U1 input and U2 output U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”. U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". U1 input and U2 output U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”. U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". U2 output “3.3 V high”, U1 keep 1.8 V with R1, and Q1 turn off, thus U1 reads “1.8 V high”.U2 output “low”, U1 keep 1.8 V with R1 firstly, but the diode inside MOSFET will pull down U1 to 0.7 V (diode voltage drops), and then cause VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low". Unused Pins Connection All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free or floating; for example, I/Os should be set to 0 or 1 (pullup or pulldown enabled on the unused I/O pins) and unused features should be disabled. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Unused Pins Connection All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free or floating; for example, I/Os should be set to 0 or 1 (pullup or pulldown enabled on the unused I/O pins) and unused features should be disabled. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free or floating; for example, I/Os should be set to 0 or 1 (pullup or pulldown enabled on the unused I/O pins) and unused features should be disabled. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free or floating; for example, I/Os should be set to 0 or 1 (pullup or pulldown enabled on the unused I/O pins) and unused features should be disabled. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. Connection of Unused Pins Pin Potential Comment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. Pin Potential Comment Pin Potential Comment PinPotentialComment PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. PAxOpenSet corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup/pulldown resistor. OPAx_IN0- Open This pin is high-impedance OPAx_IN0-OpenThis pin is high-impedance NRST VDD NRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. NRSTVDDNRST is an active-low reset signal; it must be pulled high to VCC or the device cannot start. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0. BSL invoke pin must be pulled down to avoid entering BSL mode after reset. To reduce leakage, configure the I/O as an analog input or to push-pull and to set it to 0.BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Layout Guides Power Supply Layout shows the typical parts placement and routing for the power supply layout; you must modify this appropriately for your MSPM0G part. You can optionally connect a filter inductor in series with the VCC and MCU VDD pins. This inductor is used to filter the switching noise frequency of DCDC. For the value, please refer to the data sheet of DCDC vendor. C1/C2/C3 values and layout in the MSPM0G device data sheets. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Suggested Power Supply Layout Considerations for Ground Layout System ground is the most critical area and foundation related to noise and EMI problems on the board. The most practical way to minimize these problems is to have a separate ground plane. What is Ground Noise? Each signal originating from a circuit (say Driver) has a return current flow to its source via ground path. As the frequency increases, or even for simple but high-current switching like relays, there is a voltage drop due to line impedance generating interference in the grounding scheme. The return path is always through the least resistance. For DC signals, that will be the lowest resistive path and for high frequency signals it will be the lowest impedance path. This explains how a ground plane simplifies the issue and is the key to ensuring signal integrity. It is not recommended that the digital return signals propagate inside the analog return (ground) area; therefore, the designer must split the ground plane to keep all the digital signal return loops within its ground area. This splitting should be done carefully. Many designs use a single (common) voltage regulator to generate a digital and analog supply of the same voltage level (for example, 3.3 V). You need to isolate the analog rail and digital supply rails and their respective grounds from each other. Be careful while isolating ground, as both grounds have to be shorted somewhere. shows how possible return paths for digital signals are not allowed to form a loop passing through the analog ground. On each design, decide the common point considering the component placements and so forth. Do not add any inductors (ferrite bead) or resistors (not even zero Ω) in the series with any ground trace. The impedance increases due to associated inductance at a high frequency, causing a voltage differential. Do not route a signal referenced to digital ground over analog ground or the other direction. Digital and Analog Grounds and Common Area Traces, Vias, and Other PCB Components A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45° corners. To minimize any impedance change, the best routing would be a round bend, as shown in . Poor and Correct Way of Bending Traces in Right Angle To minimize crosstalk, not only between two signals on one layer but also between adjacent layers, route them 90° to each other. More complex boards need to use vias while routing; however, care must be taken when using vias as they add additional inductance and capacitance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. When using differential signals, use vias in both traces or compensate the delay in the other trace as well. For signal traces, pay more attention to the impact of high-frequency pulse signals, especially on relatively small analog signals (like sensor signals). Too many crossovers will couple the electromagnetic noise of the high-frequency signal to the analog signal, which will result in a low signal-to-noise ratio of the signal and affect the signal quality. Therefore, it is necessary to avoid crossing when designing. But if there is indeed an unavoidable intersection, it is recommended to intersect vertically to minimize the interference of electromagnetic noise. shows how to reduce this noise. Poor and Correct Cross Traces for Analog and High-Frequency Signals How to Select Board Layers and Recommended Stack-up To reduce the reflections on high-speed signals, match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which allows all the required impedances to be realized. The minimum configuration that can be used is 2 stack-up. A 4- or 6-layer boards are required for very dense PCBs that have multiple high-speed signals. The following stack-ups are intended as 4-layer examples that can be used as a starting point for stack-up evaluation and selection. These stack-up configurations use a GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. High-speed signals on the top layer have a solid GND reference plane that helps to reduce EMC emissions. Increasing the number of layers and having a GND reference for each PCB signal layer further improves the radiated EMC performance. Four-Layer PCB Stack-up Example If the system is not very complicated, there is no high-speed signal or some sensitive analog signal, then the 2 stack-up structure is sufficient. Layout Guides Power Supply Layout shows the typical parts placement and routing for the power supply layout; you must modify this appropriately for your MSPM0G part. You can optionally connect a filter inductor in series with the VCC and MCU VDD pins. This inductor is used to filter the switching noise frequency of DCDC. For the value, please refer to the data sheet of DCDC vendor. C1/C2/C3 values and layout in the MSPM0G device data sheets. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Suggested Power Supply Layout Power Supply Layout shows the typical parts placement and routing for the power supply layout; you must modify this appropriately for your MSPM0G part. You can optionally connect a filter inductor in series with the VCC and MCU VDD pins. This inductor is used to filter the switching noise frequency of DCDC. For the value, please refer to the data sheet of DCDC vendor. C1/C2/C3 values and layout in the MSPM0G device data sheets. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Suggested Power Supply Layout shows the typical parts placement and routing for the power supply layout; you must modify this appropriately for your MSPM0G part. You can optionally connect a filter inductor in series with the VCC and MCU VDD pins. This inductor is used to filter the switching noise frequency of DCDC. For the value, please refer to the data sheet of DCDC vendor. C1/C2/C3 values and layout in the MSPM0G device data sheets. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Suggested Power Supply Layout shows the typical parts placement and routing for the power supply layout; you must modify this appropriately for your MSPM0G part. You can optionally connect a filter inductor in series with the VCC and MCU VDD pins. This inductor is used to filter the switching noise frequency of DCDC. For the value, please refer to the data sheet of DCDC vendor. C1/C2/C3 values and layout in the MSPM0G device data sheets. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3). Make all the traces direct without any vias. Keep the smallest capacitance, closest to the MCU VDD pin (C1 < C2 < C3).Make all the traces direct without any vias. Suggested Power Supply Layout Suggested Power Supply Layout Considerations for Ground Layout System ground is the most critical area and foundation related to noise and EMI problems on the board. The most practical way to minimize these problems is to have a separate ground plane. What is Ground Noise? Each signal originating from a circuit (say Driver) has a return current flow to its source via ground path. As the frequency increases, or even for simple but high-current switching like relays, there is a voltage drop due to line impedance generating interference in the grounding scheme. The return path is always through the least resistance. For DC signals, that will be the lowest resistive path and for high frequency signals it will be the lowest impedance path. This explains how a ground plane simplifies the issue and is the key to ensuring signal integrity. It is not recommended that the digital return signals propagate inside the analog return (ground) area; therefore, the designer must split the ground plane to keep all the digital signal return loops within its ground area. This splitting should be done carefully. Many designs use a single (common) voltage regulator to generate a digital and analog supply of the same voltage level (for example, 3.3 V). You need to isolate the analog rail and digital supply rails and their respective grounds from each other. Be careful while isolating ground, as both grounds have to be shorted somewhere. shows how possible return paths for digital signals are not allowed to form a loop passing through the analog ground. On each design, decide the common point considering the component placements and so forth. Do not add any inductors (ferrite bead) or resistors (not even zero Ω) in the series with any ground trace. The impedance increases due to associated inductance at a high frequency, causing a voltage differential. Do not route a signal referenced to digital ground over analog ground or the other direction. Digital and Analog Grounds and Common Area Considerations for Ground Layout System ground is the most critical area and foundation related to noise and EMI problems on the board. The most practical way to minimize these problems is to have a separate ground plane. What is Ground Noise? Each signal originating from a circuit (say Driver) has a return current flow to its source via ground path. As the frequency increases, or even for simple but high-current switching like relays, there is a voltage drop due to line impedance generating interference in the grounding scheme. The return path is always through the least resistance. For DC signals, that will be the lowest resistive path and for high frequency signals it will be the lowest impedance path. This explains how a ground plane simplifies the issue and is the key to ensuring signal integrity. It is not recommended that the digital return signals propagate inside the analog return (ground) area; therefore, the designer must split the ground plane to keep all the digital signal return loops within its ground area. This splitting should be done carefully. Many designs use a single (common) voltage regulator to generate a digital and analog supply of the same voltage level (for example, 3.3 V). You need to isolate the analog rail and digital supply rails and their respective grounds from each other. Be careful while isolating ground, as both grounds have to be shorted somewhere. shows how possible return paths for digital signals are not allowed to form a loop passing through the analog ground. On each design, decide the common point considering the component placements and so forth. Do not add any inductors (ferrite bead) or resistors (not even zero Ω) in the series with any ground trace. The impedance increases due to associated inductance at a high frequency, causing a voltage differential. Do not route a signal referenced to digital ground over analog ground or the other direction. Digital and Analog Grounds and Common Area System ground is the most critical area and foundation related to noise and EMI problems on the board. The most practical way to minimize these problems is to have a separate ground plane. What is Ground Noise? Each signal originating from a circuit (say Driver) has a return current flow to its source via ground path. As the frequency increases, or even for simple but high-current switching like relays, there is a voltage drop due to line impedance generating interference in the grounding scheme. The return path is always through the least resistance. For DC signals, that will be the lowest resistive path and for high frequency signals it will be the lowest impedance path. This explains how a ground plane simplifies the issue and is the key to ensuring signal integrity. It is not recommended that the digital return signals propagate inside the analog return (ground) area; therefore, the designer must split the ground plane to keep all the digital signal return loops within its ground area. This splitting should be done carefully. Many designs use a single (common) voltage regulator to generate a digital and analog supply of the same voltage level (for example, 3.3 V). You need to isolate the analog rail and digital supply rails and their respective grounds from each other. Be careful while isolating ground, as both grounds have to be shorted somewhere. shows how possible return paths for digital signals are not allowed to form a loop passing through the analog ground. On each design, decide the common point considering the component placements and so forth. Do not add any inductors (ferrite bead) or resistors (not even zero Ω) in the series with any ground trace. The impedance increases due to associated inductance at a high frequency, causing a voltage differential. Do not route a signal referenced to digital ground over analog ground or the other direction. Digital and Analog Grounds and Common Area System ground is the most critical area and foundation related to noise and EMI problems on the board. The most practical way to minimize these problems is to have a separate ground plane. What is Ground Noise? What is Ground Noise?Each signal originating from a circuit (say Driver) has a return current flow to its source via ground path. As the frequency increases, or even for simple but high-current switching like relays, there is a voltage drop due to line impedance generating interference in the grounding scheme. The return path is always through the least resistance. For DC signals, that will be the lowest resistive path and for high frequency signals it will be the lowest impedance path. This explains how a ground plane simplifies the issue and is the key to ensuring signal integrity.It is not recommended that the digital return signals propagate inside the analog return (ground) area; therefore, the designer must split the ground plane to keep all the digital signal return loops within its ground area. This splitting should be done carefully. Many designs use a single (common) voltage regulator to generate a digital and analog supply of the same voltage level (for example, 3.3 V). You need to isolate the analog rail and digital supply rails and their respective grounds from each other. Be careful while isolating ground, as both grounds have to be shorted somewhere. shows how possible return paths for digital signals are not allowed to form a loop passing through the analog ground. On each design, decide the common point considering the component placements and so forth. Do not add any inductors (ferrite bead) or resistors (not even zero Ω) in the series with any ground trace. The impedance increases due to associated inductance at a high frequency, causing a voltage differential. Do not route a signal referenced to digital ground over analog ground or the other direction. Digital and Analog Grounds and Common Area Digital and Analog Grounds and Common Area Traces, Vias, and Other PCB Components A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45° corners. To minimize any impedance change, the best routing would be a round bend, as shown in . Poor and Correct Way of Bending Traces in Right Angle To minimize crosstalk, not only between two signals on one layer but also between adjacent layers, route them 90° to each other. More complex boards need to use vias while routing; however, care must be taken when using vias as they add additional inductance and capacitance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. When using differential signals, use vias in both traces or compensate the delay in the other trace as well. For signal traces, pay more attention to the impact of high-frequency pulse signals, especially on relatively small analog signals (like sensor signals). Too many crossovers will couple the electromagnetic noise of the high-frequency signal to the analog signal, which will result in a low signal-to-noise ratio of the signal and affect the signal quality. Therefore, it is necessary to avoid crossing when designing. But if there is indeed an unavoidable intersection, it is recommended to intersect vertically to minimize the interference of electromagnetic noise. shows how to reduce this noise. Poor and Correct Cross Traces for Analog and High-Frequency Signals Traces, Vias, and Other PCB Components A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45° corners. To minimize any impedance change, the best routing would be a round bend, as shown in . Poor and Correct Way of Bending Traces in Right Angle To minimize crosstalk, not only between two signals on one layer but also between adjacent layers, route them 90° to each other. More complex boards need to use vias while routing; however, care must be taken when using vias as they add additional inductance and capacitance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. When using differential signals, use vias in both traces or compensate the delay in the other trace as well. For signal traces, pay more attention to the impact of high-frequency pulse signals, especially on relatively small analog signals (like sensor signals). Too many crossovers will couple the electromagnetic noise of the high-frequency signal to the analog signal, which will result in a low signal-to-noise ratio of the signal and affect the signal quality. Therefore, it is necessary to avoid crossing when designing. But if there is indeed an unavoidable intersection, it is recommended to intersect vertically to minimize the interference of electromagnetic noise. shows how to reduce this noise. Poor and Correct Cross Traces for Analog and High-Frequency Signals A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45° corners. To minimize any impedance change, the best routing would be a round bend, as shown in . Poor and Correct Way of Bending Traces in Right Angle To minimize crosstalk, not only between two signals on one layer but also between adjacent layers, route them 90° to each other. More complex boards need to use vias while routing; however, care must be taken when using vias as they add additional inductance and capacitance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. When using differential signals, use vias in both traces or compensate the delay in the other trace as well. For signal traces, pay more attention to the impact of high-frequency pulse signals, especially on relatively small analog signals (like sensor signals). Too many crossovers will couple the electromagnetic noise of the high-frequency signal to the analog signal, which will result in a low signal-to-noise ratio of the signal and affect the signal quality. Therefore, it is necessary to avoid crossing when designing. But if there is indeed an unavoidable intersection, it is recommended to intersect vertically to minimize the interference of electromagnetic noise. shows how to reduce this noise. Poor and Correct Cross Traces for Analog and High-Frequency Signals A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45° corners. To minimize any impedance change, the best routing would be a round bend, as shown in . Poor and Correct Way of Bending Traces in Right Angle Poor and Correct Way of Bending Traces in Right AngleTo minimize crosstalk, not only between two signals on one layer but also between adjacent layers, route them 90° to each other. More complex boards need to use vias while routing; however, care must be taken when using vias as they add additional inductance and capacitance, and reflections occur due to the change in the characteristic impedance. Vias also increase the trace length. When using differential signals, use vias in both traces or compensate the delay in the other trace as well. For signal traces, pay more attention to the impact of high-frequency pulse signals, especially on relatively small analog signals (like sensor signals). Too many crossovers will couple the electromagnetic noise of the high-frequency signal to the analog signal, which will result in a low signal-to-noise ratio of the signal and affect the signal quality. Therefore, it is necessary to avoid crossing when designing. But if there is indeed an unavoidable intersection, it is recommended to intersect vertically to minimize the interference of electromagnetic noise. shows how to reduce this noise. Poor and Correct Cross Traces for Analog and High-Frequency Signals Poor and Correct Cross Traces for Analog and High-Frequency Signals How to Select Board Layers and Recommended Stack-up To reduce the reflections on high-speed signals, match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which allows all the required impedances to be realized. The minimum configuration that can be used is 2 stack-up. A 4- or 6-layer boards are required for very dense PCBs that have multiple high-speed signals. The following stack-ups are intended as 4-layer examples that can be used as a starting point for stack-up evaluation and selection. These stack-up configurations use a GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. High-speed signals on the top layer have a solid GND reference plane that helps to reduce EMC emissions. Increasing the number of layers and having a GND reference for each PCB signal layer further improves the radiated EMC performance. Four-Layer PCB Stack-up Example If the system is not very complicated, there is no high-speed signal or some sensitive analog signal, then the 2 stack-up structure is sufficient. How to Select Board Layers and Recommended Stack-up To reduce the reflections on high-speed signals, match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which allows all the required impedances to be realized. The minimum configuration that can be used is 2 stack-up. A 4- or 6-layer boards are required for very dense PCBs that have multiple high-speed signals. The following stack-ups are intended as 4-layer examples that can be used as a starting point for stack-up evaluation and selection. These stack-up configurations use a GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. High-speed signals on the top layer have a solid GND reference plane that helps to reduce EMC emissions. Increasing the number of layers and having a GND reference for each PCB signal layer further improves the radiated EMC performance. Four-Layer PCB Stack-up Example If the system is not very complicated, there is no high-speed signal or some sensitive analog signal, then the 2 stack-up structure is sufficient. To reduce the reflections on high-speed signals, match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes. The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which allows all the required impedances to be realized. The minimum configuration that can be used is 2 stack-up. A 4- or 6-layer boards are required for very dense PCBs that have multiple high-speed signals. The following stack-ups are intended as 4-layer examples that can be used as a starting point for stack-up evaluation and selection. These stack-up configurations use a GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. High-speed signals on the top layer have a solid GND reference plane that helps to reduce EMC emissions. Increasing the number of layers and having a GND reference for each PCB signal layer further improves the radiated EMC performance. Four-Layer PCB Stack-up Example If the system is not very complicated, there is no high-speed signal or some sensitive analog signal, then the 2 stack-up structure is sufficient. To reduce the reflections on high-speed signals, match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which allows all the required impedances to be realized.The minimum configuration that can be used is 2 stack-up. A 4- or 6-layer boards are required for very dense PCBs that have multiple high-speed signals.The following stack-ups are intended as 4-layer examples that can be used as a starting point for stack-up evaluation and selection. These stack-up configurations use a GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. High-speed signals on the top layer have a solid GND reference plane that helps to reduce EMC emissions. Increasing the number of layers and having a GND reference for each PCB signal layer further improves the radiated EMC performance. Four-Layer PCB Stack-up Example Four-Layer PCB Stack-up ExampleIf the system is not very complicated, there is no high-speed signal or some sensitive analog signal, then the 2 stack-up structure is sufficient. Bootloader Bootloader Introduction A bootloader is a firmware IP (software shipped pre-programmed with the device) that can be used to program the SoC memories (flash and SRAM) using serial interfaces like UART or I2C. The bootloader is usually invoked after the bootcode has completed when the device is about to start the customer application. To support production programming use cases some bootloaders also offer more interfaces like SPI or CAN. A bootloader can also be used for in-field updates. Bootloader Hardware Design Considerations Physical Communication interfaces The MSPM0G bootloader (BSL) is implemented on UART and I2C serial interfaces. In MSPM0G devices, the BSL can automatically select the interface used to communicate with the device. The BSL communication pins have been pre-defined in the ROM based bootloader. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. Refer to the data sheet to find which pin has been assigned for BSL communication function before the hardware design. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Hardware Invocation The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin Bootloader Bootloader Introduction A bootloader is a firmware IP (software shipped pre-programmed with the device) that can be used to program the SoC memories (flash and SRAM) using serial interfaces like UART or I2C. The bootloader is usually invoked after the bootcode has completed when the device is about to start the customer application. To support production programming use cases some bootloaders also offer more interfaces like SPI or CAN. A bootloader can also be used for in-field updates. Bootloader Introduction A bootloader is a firmware IP (software shipped pre-programmed with the device) that can be used to program the SoC memories (flash and SRAM) using serial interfaces like UART or I2C. The bootloader is usually invoked after the bootcode has completed when the device is about to start the customer application. To support production programming use cases some bootloaders also offer more interfaces like SPI or CAN. A bootloader can also be used for in-field updates. A bootloader is a firmware IP (software shipped pre-programmed with the device) that can be used to program the SoC memories (flash and SRAM) using serial interfaces like UART or I2C. The bootloader is usually invoked after the bootcode has completed when the device is about to start the customer application. To support production programming use cases some bootloaders also offer more interfaces like SPI or CAN. A bootloader can also be used for in-field updates. Bootloader Hardware Design Considerations Physical Communication interfaces The MSPM0G bootloader (BSL) is implemented on UART and I2C serial interfaces. In MSPM0G devices, the BSL can automatically select the interface used to communicate with the device. The BSL communication pins have been pre-defined in the ROM based bootloader. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. Refer to the data sheet to find which pin has been assigned for BSL communication function before the hardware design. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Hardware Invocation The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin Bootloader Hardware Design Considerations Physical Communication interfaces The MSPM0G bootloader (BSL) is implemented on UART and I2C serial interfaces. In MSPM0G devices, the BSL can automatically select the interface used to communicate with the device. The BSL communication pins have been pre-defined in the ROM based bootloader. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. Refer to the data sheet to find which pin has been assigned for BSL communication function before the hardware design. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Physical Communication interfaces The MSPM0G bootloader (BSL) is implemented on UART and I2C serial interfaces. In MSPM0G devices, the BSL can automatically select the interface used to communicate with the device. The BSL communication pins have been pre-defined in the ROM based bootloader. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. Refer to the data sheet to find which pin has been assigned for BSL communication function before the hardware design. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset. The MSPM0G bootloader (BSL) is implemented on UART and I2C serial interfaces. In MSPM0G devices, the BSL can automatically select the interface used to communicate with the device. The BSL communication pins have been pre-defined in the ROM based bootloader. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. Refer to the data sheet to find which pin has been assigned for BSL communication function before the hardware design. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset. Note: BSL invoke pin must be pulled down to avoid entering BSL mode after reset.Note: Hardware Invocation The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin Hardware Invocation The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin The bootloader supports hardware invocation after a BOOTRST through the use of a GPIO. The BSL configuration in the NONMAIN flash memory contains the pad, pin, and polarity definition for the GPIO invocation. Devices come configured from TI for a specific GPIO and polarity, but software can change this default by modifying the GPIO pin configuration in the BSL configuration in NONMAIN flash memory. See the device specific data sheet to determine the default BSL invoke GPIO. shows an example for the GPIO pin PA18 with high level to trigger bootloader. BSL Entry Sequence at Configured GPIO Pin BSL Entry Sequence at Configured GPIO Pin References MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series MCUs Hardware Development Guide TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) References MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series MCUs Hardware Development Guide TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series MCUs Hardware Development Guide TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series MCUs Hardware Development Guide TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0G350x Mixed-Signal Microcontrollers data sheet MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series MCUs Hardware Development Guide MSPM0 L-Series MCUs Hardware Development Guide TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TLIN1021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake data sheet (Rev. B) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) TCAN1042-Q1Automotive Fault Protected CAN Transceiver with CAN FD data sheet (Rev. D) Revision History yes March 2023 June 2023 A B Revision History yes March 2023 June 2023 A B yes March 2023 June 2023 A B yesMarch 2023June 2023AB IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI’s Terms of Saleti.com TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated).
Figure 8-1 Suggested ODIO Circuit