SLAAE76B march   2023  – june 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0G Hardware Design Check List
  5. 2 Power Supplies in MSPM0G Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug port pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    6. 8.6 Communicate With a 1.8-V Device Without a Level Shifter
    7. 8.7 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11References
  15. 12Revision History

2.2 Analog Power Supply

Analog Mux VBOOST

The VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog muxes in COMP, GPAMP, and OPA, if present on a device. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range.

Enabling and Disabling VBOOST

SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters:

  1. The COMP, OPA, and GPAMP peripheral PWREN settings
  2. The MODE setting of any COMP which is enabled (FAST vs. ULP mode).
  3. The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL.

VBOOST is disabled by default following a SYSRST. It is not necessary for application software to enable the VBOOST circuit before using the COMP, OPA, or GPAMP. When a COMP, OPA, or the GPAMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral.

Note: The VBOOST circuit has a startup time requirement (12 μs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP, OPA, or GPAMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time.

Bandgap Reference

The PMU provides a temperature and supply voltage stable bandgap voltage reference, which is used by the device for internal functions including:

  • Driving the brownout reset circuit thresholds.
  • Setting the output voltage for the core regulator.
  • Driving the on-chip VREF levels for on-chip analog peripherals.

The bandgap reference is enabled in RUN, SLEEP, STOP modes. It operates in a sampled mode in STANDBY to reduce power consumption. It is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically so that no user configuration is required.