SLAAED9 November 2023 TAA5412-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1
This register is the interrupt configuration register.
Bit | Field | Type(1) | Reset | Description |
---|---|---|---|---|
7 | INT_POL | R/W | 0b | Interrupt polarity 0b = Active low (IRQZ) 1b = Active high (IRQ) |
6-5 | INT_EVENT[1:0] | R/W | 00b | Interrupt event
configuration 0d = INT asserts on any unmasked latched interrupts event 1d = INT asserts on any unmasked live interrupts event 2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event 3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event |
4-3 | PD_ON_FLT_CFG[1:0] | R/W | 00b | Power down configuration
during fault for CHx and MCBIAS 0d = Faults are not considered for power down 1d = Only unmasked faults are considered for power down 2d = All faults are considered for power down 3d = Reserved |
2 | LTCH_READ_CFG | R/W | 0b | Interrupt latch registers
readback configuration 0b = All interrupts can be read through the LTCH registers 1b = Only unmasked interrupts can be read through the LTCH registers |
1 | PD_ON_FLT_RCV_CFG | R/W | 0b | Configuration for power down
ADC channels on fault 0b = Auto recovery, ADC channels are powered-up again when fault goes away 1b = Manual recovery, ADC channels are not powered up again when fault goes away |
0 | LTCH_CLR_ON_READ | R/W | 0b | Configuration for clearing
LTCH register bits 0 = LTCH register bits are cleared on register read only if live status is zero 1 = LTCH register bits are cleared on register read irrespective of live status |
In addition to the mask settings, DIAG_CFG10, P1_R80 allows the user to select which MICBIAS faults are used for the power down of MICBIAS and all ADC channels.