SLAAEF9 November 2023 MSPM0C1104 , MSPM0G3507 , MSPM0L1306
Different clock signals can be divided to source other clocks and be distributed across the multitude of peripherals.
Clock Description | RL78 Clock | MSPM0 Clock | |
---|---|---|---|
External digital clock input | High frequency | EXCLK (fEX) | HFCLK_IN |
Low frequency | EXCLKS (fEXS) | LFCLK_IN | |
High-frequency external clock | fMX | HFCLK | |
Low-frequency external clock | fSUB (1) | Selection of LFCLK_IN and LFXT | |
PLL circuit output clock | fPLL | SYSPLLCLK0, SYSPLLCLK1, SYSPLLCLK2x (2) |
|
Main system clock | fMAIN (3) | MCLK, ULPCLK (4) (BUSCLK) | |
High-frequency clock for CPU/peripherals | fMAIN or fMP/n (5) | Selection of HSCLK (6) and SYSOSC | |
Low-frequency clock for CPU/peripherals | fSL | LFCLK (fixed 32 kHz) | |
Source CPU | fCLK | CPUCLK | |
Clock for most peripheral hardware | fCLK | MCLK, ULPCLK | |
Available clock for high-speed peripherals | fMX, fIH, fMAIN, fPLL, fMP, fCLK | MCLK | |
Available clock for low-speed low-power peripherals | fSUB,fIL, fSL, fCLK | ULPCLK | |
Fixed frequency clock | N/A | MFCLK: 4 MHz, synchronized to MCLK | |
MFPCLK: 4 MHz |
Peripheral | RL78 | MSPM0 |
---|---|---|
Real-time clock (RTC) | fIH, fIL, fMX, fSUB, fCLK | LFCLK (LFOSC, LFXT) |
UART | fCLK | BUSCLK, MFCLK, LFCLK |
SPI/CSI (simplified SPI) | fCLK | BUSCLK, MFCLK, LFCLK |
I2C | fCLK | BUSCLK, MFCLK |
CAN | fMX, fMP, fCLK | PLLCLK1, HFCLK |
ADC | fCLK | ULPCLK, HFCLK, SYSOSC |
TIMERS | fHOCO, fIL, fMX, fSL, fPLL, fMP, fCLK, fTMKB2 (1) | BUSCLK, MFCLK, LFCLK |
COMPARATOR | fPLL, fCLK | ULPCLK |