SLAAEG4 October 2023 MSPM0C1104 , MSPM0L1306
The MSPM0 C-series microcontroller (MCU) portfolio offers a wide variety of low cost 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement and control applications. This application note covers information needed for hardware development with MSPM0 C-series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance.
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Table 1-1 describes the main signal that needs to be checked during the MSPM0C hardware design process. The following sections provide more details.
Pin (1) | Description | Requirements |
---|---|---|
VDD | Power supply positive pin | Place 10-µF and 100-nF capacitors between VDD and VSS, and keep those part close to VDD and VSS. |
VSS | Power supply negative pin | |
NRST | Reset pin | Connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor. |
SWCLK | Serial wire clock from debug probe | Internal pulldown to VDD, does not need any external part. |
SWDIO | Bidirectional (shared) serial wire data | Internal pullup to VSS, does not need any external part. |
PA0, PA1 | Open-drain I/O | Pull-up resistor required for output high |
PAx (exclude PA0, PA1) | General-purpose I/O | Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. |
TI recommends connecting a combination of a 10-μF and a 0.1-nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins. Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the decoupled pins (within a few millimeters).
The NRST reset pin is required to connect an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor.
For 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for inter-integrated circuit (I2C) and universal asynchronous receiver/transmitter (UART) functions if the ODIO are used.
Power is supplied to the device through the VDD and VSS connections. The device supports operation with a supply voltage of 1.62 V to 3.6 V and can start with a 1.62-V supply. The power management unit (PMU) generates the regulated core supplies for the device and provides supervision of the external supply. It also contains a bandgap voltage reference used by the PMU and other analog peripherals. VDD is used directly to provide the IO supply (VDDIO) and the analog supply (VDDA). VDDIO and VDDA are internally connected to VDD so that additional power supply pins are not required (see the device-specific data sheet for details).
There is an internal low-dropout linear voltage regulator to generate a 1.35-V supply rail to power the device core. The core regulator is active in all power modes except for SHUTDOWN. In all other power modes (RUN, SLEEP, STOP, and STANDBY) the drive strength of the regulator is configured automatically to support the max load current of each mode. This reduces the quiescent current of the regulator when using low power modes, improving low power performance.