SLAAEG6A November 2023 – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5142 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5242 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242
Secondary ASI needs to be Target, Primary ASI can be either Controller, Target, or disabled Secondary ASI BCLK provided by user is used as Reference clock for the PLL or Audio Root Source clock.
Configurations to enter this mode include:
Mode | Configuration |
---|---|
CLK_SRC_SEL | (B0_P0_R52[3:1]) – must be 3’d0 |
CUSTOM_CLK_CFG register | (B0_P0_R50[0]) – must be 1’b0 |
SASI_SAMP_RATE | (B0_P0_R51[7:2]) |
SASI_FS_BCLK_RATIO | {B0_P0_R58[5:0], B0_P0_R59 |
Must be configured as 0 for the device to auto detect |
Controller Mode: To operate primary ASI as Controller Mode, specify the Fs Rate as well as the BCLK to Fs ratio.
Mode | Configuration |
---|---|
PASI_MST_CFG | B0_P0_R55[4] |
1 to operate Primary ASI as Controller 0 to operate Primary ASI as Target (Default) | |
PASI_FS_BCLK_RATIO | B0_P0_R56[5:0], B0_P0_R57 |
PASI_SAMP_RATE | B0_P0_R50[7:2] |
FS_MODE | B0_P0_R55[0] |
Must be configured as 0 for the device to auto detect |