SLAAEG6 November 2023 TAA5212 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5212 , TAD5212-Q1
Primary ASI should be Target, Secondary ASI can be either Controller, Target or disabled Primary ASI BCLK provided by user is used as Reference clock for the PLL or Audio Root Source clock.
I2C Bits | |
---|---|
CLK_SRC_SEL | (B0_P0_R52[3:1]) – must be 3’d0 |
CUSTOM_CLK_CFG register | (B0_P0_R50[0]) – must be 1’b0 |
PASI_SAMP_RATE | (B0_P0_R50[7:2]) |
PASI_FS_BCLK_RATIO | {B0_P0_R56[5:0], B0_P0_R57 |
Must be configured as 0 for the device to auto detect | |
PASI_MST_CFG | B0_P0_R55[4] |
0 to operate Primary ASI as Target(Default) |
To operate Secondary ASI as Controller Mode, we need to specify the Fs Rate as well as the BCLK to Fs ration
Mode | Controller |
---|---|
SASI_MST_CFG | B0_P0_R55[3] |
1 to operate Secondary ASI as Controller, 0 to operate Secondary ASI as Target(Default) | |
SASI_FS_BCLK_RATIO | B0_P0_R58[5:0], B0_P0_R59 |
SASI_SAMP_RATE | B0_P0_R51[7:2] |
FS_MODE | B0_P0_R55[0] |
1 to generate Fsync frequency as a multiple of 44.1 KHz , 0 to generate Fsync frequency as a multiple of 48 KHz (Default) |