SLAAEG6A November   2023  – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5142 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5242 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
      1. 3.5.1 Semi-Automatic Mode
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Clocking in Hardware Controlled Devices
  8. 5Revision History

3.3 Auto MCLK Ratio

MCLK supplied at the input Pad is to be user as audio source, Frequency of MCLK is Integer multiple of Fsync frequency. Both the Primary FSYNC can be used as timing reference. Auto detection is enabled in this mode.

Both Primary and Secondary ASI’s can be configured either Controller or Target. At least one can be enabled. MCLK provided by the user is used as Reference clock for the PLL or Audio Root Source clock

Table 3-5 Register Settings to Setup Mode
Mode Configuration
CLK_SRC_SEL (B0_P0_R52[3:1]) – must be 3’d1 or 3d3
Frequency that is integer multiple of PASI Fsync, when CLK_SRC_SEL is configured as 3’d1.
Frequency that is integer multiple of SASI Fsync, when CLK_SRC_SEL is configured as 3’d3.
CUSTOM_CLK_CFG register (B0_P0_R50[0]) – must be 1’b0
PASI/SASI_SAMP_RATE (B0_P0_R50[7:2]

B0_P0_R51[7:2])

FS_MCLK_RATIO {B0_P0_R53[5:0], B0_P0_R54}
Must be configured as 0 for the device to auto detect

Controller Mode: To operate primary ASI as Controller Mode, the Fs Rate needs to be specified as well as the BCLK to Fs ration

Table 3-6 Register Setting to Setup as Controller
Mode Configuration
PASI_MST_CFG B0_P0_R55[4]
1 to operate Primary ASI as Controller, 0 to operate Primary ASI as Target (Default)
SASI_MST_CFG B0_P0_R55[3]
1 to operate Secondary ASI as Controller , 0 to operate Secondary ASI as Target(Default)
FS_MCLK_RATIO B0_P0_R53[5:0], B0_P0_R54
PASI_SAMP_RATE B0_P0_R50[7:2]
SASI_SAMP_RATE B0_P0_R51[7:2]
FS_MODE B0_P0_R55[0]
1 to generate Fsync frequency as a multiple of 44.1 KHz , 0 to generate Fsync frequency as a multiple of 48 KHz (Default)