SLAAEI9 December 2023 MSPM0C1103 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1228
Different clock signals can be divided to source other clocks and be distributed across the multitude of peripherals.
Clock Description | STM8L Clock | STM8S Clock | MSPM0L/C Clock | |
---|---|---|---|---|
External digital clock input | High frequency | External source: up to 16 MHz(1) | HSE Ext: up to 24 MHz(1) | N/A |
Low frequency | External source: 32.768 kHz(1) | N/A | N/A | |
High-frequency sources for main clock | HSI, HSE | fHSE, fHSIDIV | SYSOSC | |
Low-frequency sources for main clock | LSI, LSE | fLSI | LFCLK (fixed 32 kHz) | |
Main system clock | SYSCLK, fMASTER | fMASTER | MCLK, ULPCLK (BUSCLK)(2) | |
Source CPU | SYSCLK, fMASTER | fCPU | CPUCLK | |
Clock for most peripheral hardware | PCLK (SYSCLK), fMASTER | fMASTER | MCLK, ULPCLK(2) | |
Peripheral specific clock | BEEPCLK, IWDGCLK, RTCCLK, fLSI, fHSI/2(3) | N/A | ADCCLK | |
Fixed frequency clock | N/A | N/A | MFCLK: 4 MHz, synchronized to MCLK/ULPCLK |
Peripheral | STM8L/S | MSPM0L/C |
---|---|---|
UART/USART | SYSCLK, fMASTER | SYSCLK, MFCLK, LFCLK |
SPI | SYSCLK, fMASTER | SYSCLK, MFCLK, LFCLK |
I2C | SYSCLK, fMASTER | BUSCLK, MFCLK |
ADC | PCLK or PCLK/2(1), fADC (fMASTER divided by 2 to 18) | ADCCLK (sourced by ULPCLK or SYSOSC) |
TIMERS | SYSCLK, fMASTER, fMASTER/DIV | BUSCLK, MFCLK, LFCLK |
COMPARATOR | PCLK, fMASTER(2) | BUSCLK |
WATCHDOG | LSI, SYSCLK, fCPU(3) | LFCLK |