Low-Frequency Subsystem and VBAT Feature in MSPM0L222X
Abstract
The Low-Frequency Subsystem (LFSS), is a new
feature set in the MSPM0Lx22x device family that features a
real-time clock (RTC), low-frequency crystal (LFXT),
low-frequency oscillator (LFOSC), and scratchpad memory
(SPM). The LFSS is powered by a separate power domain named
VBAT Power Domain which allows the
peripherals in the LFSS to continue running when the main
VDD power is lost. This application note discusses how the
LFSS and VBAT domain is used in an application. Find used
examples under SDK with this address:
C:\ti\mspm0_sdk_x_xx_xx_xx_internal\examples\nortos\LP_MSPM0L2228\driverlib.
Trademarks
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1 Introduction
The Low-Frequency Sub-System (LFSS) combines several functional peripherals within the subsystem. In the LFSS intellectual property (IP), all the functional peripherals are clocked by low-frequency clock (LFCLK) which activates during low-power mode. The battery backup domain is initially powered by the power input VDD and compensates power loss by drawing power from the battery to keep running the functional peripherals at a frequency rate of 32kHz with the intention of long-term time keeping. The following sections provide brief descriptions for each of the LFSS peripherals. See also the MSPM0 L-Series 32MHz Microcontrollers Technical Reference Manual.
2 Low-Frequency Subsystem Introduction
Figure 2-1 shows the block diagram for the LFSS. Each part of the LFSS is thoroughly explained in this document.
Figure 2-1 LFSS Block Diagram2.1 Resetting LFSS IP Using VBAT
The LFSS IP has a reset generation circuit, which is implemented in the VBAT domain. The two related subcircuits that are related to the reset of LFSS are the power-on reset (POR) and the brownout reset (BOR). The POR is a Vth based supply voltage detector on the VBAT domain that is used to reset the power management unit (PMU) and start-up the cold boot sequence. The BOR is a reference-based voltage monitor that enables the LDO when the VBAT supply is large enough to operate the LDO safely. On initial VBAT supply power up and the enable of VRTC LDO, the VRTC detects an initial reset. Once the reset is deasserted, the VRTC domain does not detect another reset unless the power supply drops below the BOR level. The POR and BOR does not reset VRTC domain.
2.2 Power Domain Supply Detection
The LFSS IP needs to monitor the presence of the VBAT supply and the VDD supply independently as there was no dedicated always-on domain that can indicate which domain is powered and which is not. The VDD and VBAT can be powered with different voltage levels. For example, the system on chip (SoC) can be powered by a 1.8V LDO from the system LDO on the PCB, while VBAT is supplied from a 3V coin cell battery. Alternatively, in the other direction the SoC can be powered by the LDO system with 3.3V.
Figure 2-1 shows that the power domain sensing, isolation, and reset generation are very similar for both power domains. Each domain has a POR and BOR circuit. The isolation and reset signal for the sub-power domain (VCORE, VRTC) are generated by a reset latch - set latch (RS-latch). The isolation and reset signal are actively asserted (SET) with the detection of a POR or BOR event. The RS-latch is cleared once the subdomain voltage comparator gives an OK signal for the corresponding domain.
