SLAAEN0 September   2024 MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Low-Frequency Subsystem Introduction
    1. 2.1 Resetting LFSS IP Using VBAT
    2. 2.2 Power Domain Supply Detection
      1. 2.2.1 Start-Up Sequences
      2. 2.2.2 LFSS IP Behavior
    3. 2.3 LFXT, LFOSC
    4. 2.4 Independent Watchdog Timer (IWDT)
    5. 2.5 Tamper I/O
      1. 2.5.1 IOMUX Mode
      2. 2.5.2 Tamper Mode
        1. 2.5.2.1 Tamper Event Detection
        2. 2.5.2.2 Timestamp Event Output
        3. 2.5.2.3 Heatbeat Generator
    6. 2.6 Scatchpad Memory (SPM)
    7. 2.7 Real-Time Clock (RTC)
    8. 2.8 VBAT Charging Mode
  6. 3Application Examples
    1. 3.1 Tamper I/O Heartbeat Example
    2. 3.2 RTC Tamper I/O Timestamp Event Example
    3. 3.3 Supercapacitor Charging Example
    4. 3.4 LFOSC Transition Back to LFXT Example
    5. 3.5 RTC_A Calibration
      1. 3.5.1 Peripheral ADC 12
      2. 3.5.2 RTC_A

2.2.2 LFSS IP Behavior

The power loss of VDD is not going to happen instantaneously due to the required system-level decoupling capacitors. As VDD supply ramps down and reaches the BOR level (1.62V), the VCORE LDO gets disabled and VCORE_ISO latch gets set. Eventually the VDD level drops below the POR level and resets the VDD domain of the SoC. This is detected by the VDD detect circuit which is powered by the VBAT domain.

The shutdown mode sequence is different since the VDD domain stays powered. The shutdown mode is initiated by software and is stored in the shutdown mode register in the VDD domain. This disables the LDO and sets the VCORE_ISO latch. On a wakeup from shutdown mode, the SoC PMU reenables the REF system, BOR, and the LDO.

There are certain minimum decoupling capacitors required on the VBAT supply pin, mainly for noise immunity and to supply peak currents during switching activity on a high-impedance power source. Due to the required decoupling capacitor, the loss of the VBAT supply happens in a ramp. Due to the ramp, the VBAT-BOR circuit detects the loss of the VBAT domain first and then sets the VRTC_ISO latch. Meanwhile the circuit disables the VBAT-PMU, the VRTC_ISO isolation signal transverses through the VDD domain and isolates all signals from the VRTC domain.