SLAAEN0 September   2024 MSPM0L1227 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Low-Frequency Subsystem Introduction
    1. 2.1 Resetting LFSS IP Using VBAT
    2. 2.2 Power Domain Supply Detection
      1. 2.2.1 Start-Up Sequences
      2. 2.2.2 LFSS IP Behavior
    3. 2.3 LFXT, LFOSC
    4. 2.4 Independent Watchdog Timer (IWDT)
    5. 2.5 Tamper I/O
      1. 2.5.1 IOMUX Mode
      2. 2.5.2 Tamper Mode
        1. 2.5.2.1 Tamper Event Detection
        2. 2.5.2.2 Timestamp Event Output
        3. 2.5.2.3 Heatbeat Generator
    6. 2.6 Scatchpad Memory (SPM)
    7. 2.7 Real-Time Clock (RTC)
    8. 2.8 VBAT Charging Mode
  6. 3Application Examples
    1. 3.1 Tamper I/O Heartbeat Example
    2. 3.2 RTC Tamper I/O Timestamp Event Example
    3. 3.3 Supercapacitor Charging Example
    4. 3.4 LFOSC Transition Back to LFXT Example
    5. 3.5 RTC_A Calibration
      1. 3.5.1 Peripheral ADC 12
      2. 3.5.2 RTC_A

Power Domain Supply Detection

The LFSS IP needs to monitor the presence of the VBAT supply and the VDD supply independently as there was no dedicated always-on domain that can indicate which domain is powered and which is not. The VDD and VBAT can be powered with different voltage levels. For example, the system on chip (SoC) can be powered by a 1.8V LDO from the system LDO on the PCB, while VBAT is supplied from a 3V coin cell battery. Alternatively, in the other direction the SoC can be powered by the LDO system with 3.3V.

Figure 2-1 shows that the power domain sensing, isolation, and reset generation are very similar for both power domains. Each domain has a POR and BOR circuit. The isolation and reset signal for the sub-power domain (VCORE, VRTC) are generated by a reset latch - set latch (RS-latch). The isolation and reset signal are actively asserted (SET) with the detection of a POR or BOR event. The RS-latch is cleared once the subdomain voltage comparator gives an OK signal for the corresponding domain.