SLAAEO5 September   2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to the Debug Subsystem and MSPM0
    1. 1.1 Access Ports of MSPM0
      1. 1.1.1 Advance High-Performance Bus Access Port
      2. 1.1.2 Configuration Access Port
      3. 1.1.3 Security Access Port
      4. 1.1.4 EnergyTrace Access Port
      5. 1.1.5 Power Access Port
    2. 1.2 Behaviors With the MSPM0 in a Blank/Low-Power State
  5. 2Proper SWD Initialization Sequence
  6. 3PWR-AP
    1. 3.1 Enabling Low-Power Mode Debugging With MSPM0
    2. 3.2 Modifying the Reset Behavior of MSPM0
      1. 3.2.1 Wait for Debug
      2. 3.2.2 Halt on Reset
      3. 3.2.3 INRST Behavior
    3. 3.3 Register View
  7. 4SEC-AP
    1. 4.1 DSSM Commands
      1. 4.1.1 Factory Reset
      2. 4.1.2 Mass Erase
      3. 4.1.3 Password Authentication
      4. 4.1.4 Data Exchange
      5. 4.1.5 Wait for Debug
      6. 4.1.6 Custom DSSM Command
    2. 4.2 DSSM Flow
    3. 4.3 Register View
  8. 5Understanding Flash in MSPM0
    1. 5.1 Protection of Flash Memory Across MSPM0
    2. 5.2 Clearing the STATCMD Register
    3. 5.3 Ideal Programming Flow for MSPM0
  9. 6The Resets of MSPM0
  10. 7Summary
  11. 8References

4.1.5 Wait for Debug

When the command for the "Wait for Debug" command is sent to the mailbox and processed. Similar to wait for debug described previously in Section 3.2, it resets the peripherals defined by the reset level and then forces the device into the reset handler. However, when performing the wait for debug sequence via the mailbox, it requires the INRST bit to be cleared after executing the command to fully execute the command the command.