SLAAEO5 September   2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to the Debug Subsystem and MSPM0
    1. 1.1 Access Ports of MSPM0
      1. 1.1.1 Advance High-Performance Bus Access Port
      2. 1.1.2 Configuration Access Port
      3. 1.1.3 Security Access Port
      4. 1.1.4 EnergyTrace Access Port
      5. 1.1.5 Power Access Port
    2. 1.2 Behaviors With the MSPM0 in a Blank/Low-Power State
  5. 2Proper SWD Initialization Sequence
  6. 3PWR-AP
    1. 3.1 Enabling Low-Power Mode Debugging With MSPM0
    2. 3.2 Modifying the Reset Behavior of MSPM0
      1. 3.2.1 Wait for Debug
      2. 3.2.2 Halt on Reset
      3. 3.2.3 INRST Behavior
    3. 3.3 Register View
  7. 4SEC-AP
    1. 4.1 DSSM Commands
      1. 4.1.1 Factory Reset
      2. 4.1.2 Mass Erase
      3. 4.1.3 Password Authentication
      4. 4.1.4 Data Exchange
      5. 4.1.5 Wait for Debug
      6. 4.1.6 Custom DSSM Command
    2. 4.2 DSSM Flow
    3. 4.3 Register View
  8. 5Understanding Flash in MSPM0
    1. 5.1 Protection of Flash Memory Across MSPM0
    2. 5.2 Clearing the STATCMD Register
    3. 5.3 Ideal Programming Flow for MSPM0
  9. 6The Resets of MSPM0
  10. 7Summary
  11. 8References

4.3 Register View

Table 4-2 SEC-AP Register View
APSEL AP-NAME ADDR BANK INDEX REG-NAME BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2 SEC 0x00 0 0 TXDATA TX DATA
0x04 0 1 TXCTL TX CONTROL TX VLD
0x08 0 2 RXDATA RX DATA
0x0C 0 3 RXCTL RESERVED RX CONTROL RX VLD
0xFC 15 3 IDR Access point ID