SLAAEO5 September 2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105
It is also possible for the user to create their own DSSM command and have it perform actions defined by the user. This can be done by having the debugger communicate to the M0+ core through the TXDATA and TXCTL. The core can then receive messages from the debugger and send responses back by using the RXDATA and RXCTL registers for the debugger to read. It is also possible to configure CPU interrupt events for activity seen in the TX_DATA buffer, RX_DATA buffer, and DAP connection.