Figure 1-1 shows the system schematic diagram of SAR ADC. SAR ADC controls the switching of multiple switches (12 switches in this case) to perform capacitive voltage division on VREF and obtain different analog voltage output results. Compare the analog voltage with the input sampling signal, and the output of the comparator is used to adjust the on/off state of the switch, ultimately making the simulated voltage obtained by VREF voltage division as close as possible to the input voltage. The actual comparison process is achieved by using the binary method to approximate VREF division for the VIN, thus requiring 12 cycles for data conversion. When considering the ADC triggering, signal sampling and holding time, the actual SAR ADC conversion process takes more than 12 cycles (It takes 14 conversion cycles in MSPM0 G-Series).

Figure 1-1 Principle Block Diagram of SAR ADC Based on CDAC