Figure 1-1 shows the system schematic diagram of SAR ADC. SAR ADC controls the switching of multiple switches (12 switches in this case) to perform capacitive voltage division on VREF and obtain different analog voltage output results. Compare the analog voltage with the input sampling signal, and the output of the comparator is used to adjust the on/off state of the switch, ultimately making the simulated voltage obtained by VREF voltage division as close as possible to the input voltage. The actual comparison process is achieved by using the binary method to approximate VREF division for the VIN, thus requiring 12 cycles for data conversion. When considering the ADC triggering, signal sampling and holding time, the actual SAR ADC conversion process takes more than 12 cycles (It takes 14 conversion cycles in MSPM0 G-Series).

Figure 1-1 Principle Block Diagram of SAR ADC Based on CDAC

• Differential Nonlinearity Error (DNL)

  Differential nonlinearity error is the maximum deviation between the actual step and the ideal step during the ADC analog-to-digital conversion process, where the ideal step refers to 1LSB. DNL exceeding 1LSB results in missing codes in the ADC digital result, meaning that a certain digital code will disappear in the output result.

  Equation 1. $\mathrm{DNL}=\mathrm{Actual} \mathrm{Step}-1\mathrm{LSB}$
• Integral Nonlinearity Error (INL)

  Integral nonlinear error is the deviation between a certain conversion voltage and the ideal conversion voltage during the ADC conversion process, which reflects the integration of DNL. The measurement of this value was carried out after compensating for offset error and gain error. By measuring the conversion voltage of each digital code, the INL of each code point can be obtained. Only the maximum INL value is provided in the ADC data manual.

  Equation 2. $\mathrm{INL}=\mathrm{the} \mathrm{kth} \mathrm{actual} \mathrm{conversion} \mathrm{voltage}-(\mathrm{k}-0.5)\mathrm{LSB}$
• Offset Error (EO)

  Offset error is the deviation between the voltage at the first actual conversion and the first ideal conversion when the ADC increases from a low voltage. The first conversion occurs when the digital ADC output changes from 0 to 1. For an ideal ADC, when the analog input is between 0.5 LSB and 1.5 LSB, the digital output should be 1, thus the first ideal conversion occurs at 0.5 LSB. So offset error calculation formula is:

  Equation 3. $\mathrm{EO}=\mathrm{the} \mathrm{first} \mathrm{actual} \mathrm{conversion} \mathrm{voltage}-0.5\mathrm{LSB}$
• Gain Error (EG)

  Gain error is the voltage deviation between the last actual conversion voltage and the last ideal conversion voltage, and this value is measured after correcting the offset error. Taking a 12-bit ADC as an example, the last actual conversion occurs when output digital result changes from 0xFFE to 0xFFF, which corresponding to a voltage of VREF+ - 0.5 LSB. Therefore, the calculation formula is:

  Equation 4. $\mathrm{EG}=\mathrm{the} \mathrm{last} \mathrm{actual} \mathrm{conversion} \mathrm{voltage}- ({\mathrm{VREF}}_{+}-0.5\mathrm{LSB})$