SLAAEO8 October   2024 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519 , MSPM0L1105

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1ADC Introduction
    1. 1.1 SAR ADC Principle
    2. 1.2 ADC Parameters
      1. 1.2.1 Static Parameters
      2. 1.2.2 Dynamic Parameters
        1. 1.2.2.1 AC Parameters
        2. 1.2.2.2 DC Parameters
  5. 2ADC Noise Analysis
    1. 2.1 ADC Noise Classification
      1. 2.1.1 ADC Noise
      2. 2.1.2 Reference Noise
      3. 2.1.3 Power Supply Noise
      4. 2.1.4 ADC Input Noise
      5. 2.1.5 Clock Jitter
    2. 2.2 How to Reduce Noise
      1. 2.2.1 Reducing Input Noise Through RC Filtering
      2. 2.2.2 Layout Suggestions
      3. 2.2.3 Improving Signal-to-Noise Ratio
      4. 2.2.4 Choose a Suitable Reference Voltage Source
      5. 2.2.5 Software Methods for Reducing Noise
  6. 3ADC Oversampling
    1. 3.1 Sampling Rate
    2. 3.2 Extraction
    3. 3.3 Application Conditions
  7. 4ADC Application Based on MSPM0
    1. 4.1 ADC Configuration of MSPM0
    2. 4.2 ADC DC Test Based on MSPM0G3507 ADC EVM Board
      1. 4.2.1 Software/Hardware Configuration
        1. 4.2.1.1 Hardware
        2. 4.2.1.2 Software
      2. 4.2.2 Test Result
      3. 4.2.3 Result Analysis and Conclusion

2.1 ADC Noise Classification

The following figure shows the block diagram of an ADC system, which shows the signal chain of ADC sampling data and the necessary signal inputs for the operation of the ADC module. Each link may introduce noise to the ADC system, so the sources of ADC system noise include sensor noise, operational amplifier noise, ADC noise, power supply noise, reference voltage noise, and clock jitter noise.

The sensor noise and operational amplifier usage vary greatly depending on the application scenario, and are greatly affected by the layout. This article classifies them as input noise of the ADC. Figure 2-1introduces the sources of noise in each stage separately.

Schematic Diagram of ADC Noise Sources Figure 2-1 Schematic Diagram of ADC Noise Sources