SLAS898B January   2014  – April 2015 TAS2552

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements/Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  General I2C Operation
      2. 7.3.2  Single-Byte and Multiple-Byte Transfers
      3. 7.3.3  Single-Byte Write
      4. 7.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 7.3.5  Single-Byte Read
      6. 7.3.6  Multiple-Byte Read
      7. 7.3.7  PLL
      8. 7.3.8  Gain Settings
      9. 7.3.9  Class-D Edge Rate Control
      10. 7.3.10 Battery Tracking AGC
      11. 7.3.11 Configurable Boost Current Limit (ILIM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Digital I/O Interface
        1. 7.4.1.1 Right-Justified Mode
        2. 7.4.1.2 Left-Justified Mode
        3. 7.4.1.3 I2S Mode
        4. 7.4.1.4 Audio Data Serial Interface Timing (I2S, Left-Justified, Right-Justified Modes)
        5. 7.4.1.5 DSP Mode
        6. 7.4.1.6 DSP Timing
      2. 7.4.2 TDM Mode
      3. 7.4.3 PDM Mode
        1. 7.4.3.1 DOUT Timing - PDM Output Mode
    5. 7.5 Register Map
      1. 7.5.1  Register Map Summary
      2. 7.5.2  Register 0x00: Device Status Register
      3. 7.5.3  Register 0x01: Configuration Register 1
      4. 7.5.4  Register 0x02: Configuration Register 2
      5. 7.5.5  Register 0x03: Configuration Register 3
      6. 7.5.6  Register 0x04: DOUT Tristate Mode
      7. 7.5.7  Register 0x05: Serial Interface Control Register 1
      8. 7.5.8  Register 0x06: Serial Interface Control Register 2
      9. 7.5.9  Register 0x07: Output Data Register
      10. 7.5.10 Register 0x08: PLL Control Register 1
      11. 7.5.11 Register 0x09: PLL Control Register 2
      12. 7.5.12 Register 0x0A: PLL Control Register 3
      13. 7.5.13 Register 0x0B: Battery Tracking Inflection Point Register
      14. 7.5.14 Register 0x0C: Battery Tracking Slope Control Register
      15. 7.5.15 Register 0x0D: Reserved Register
      16. 7.5.16 Register 0x0E: Battery Tracking Limiter Attack Rate and Hysteresis Time
      17. 7.5.17 Register 0x0F: Battery Tracking Limiter Release Rate
      18. 7.5.18 Register 0x10: Battery Tracking Limiter Integration Count Control
      19. 7.5.19 Register 0x11: PDM Configuration Register
      20. 7.5.20 Register 0x12: PGA Gain Register
      21. 7.5.21 Register 0x13: Class-D Edge Rate Control Register
      22. 7.5.22 Register 0x14: Boost Auto-Pass Through Control Register
      23. 7.5.23 Register 0x15: Reserved Register
      24. 7.5.24 Register 0x16: Version Number
      25. 7.5.25 Register 0x17: Reserved Register
      26. 7.5.26 Register 0x18: Reserved Register
      27. 7.5.27 Register 0x19: VBAT Data Register
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application - Digital Audio Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Audio Input/Output
          2. 8.2.1.2.2 Mono/Stereo Configuration
          3. 8.2.1.2.3 Boost Converter Passive Devices
          4. 8.2.1.2.4 EMI Passive Devices
          5. 8.2.1.2.5 Miscellaneous Passive Devices
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Typical Application - Analog Audio Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Audio Input/Output
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Typical Application - Maximum Output Power, Analog Audio Input
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Performance Plots
    3. 8.3 Initialization
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
    2. 9.2 Power Supply Sequencing
    3. 9.3 Boost Supply Details
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Dimensions
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

30-Ball WCSP
YFF Package
(Top View)
TAS2552 Pinout.gif

Pin Functions

TERMINAL INPUT/OUTPUT/POWER DESCRIPTION
NAME BALL WCSP
PGND A1 P Power ground. Connect to high current ground plane.
OUT– A2 O Inverting Class D output.
OUT+ A3 O Non-inverting Class D output.
PVDD A4 P Class-D power supply. Connected internally to VBOOST – do not drive this terminal externally.
VBOOST A5 P 8.5 V boost output. Connected internally to PVDD – do not drive this terminal externally.
BIAS B1 O Mid-rail reference for Class D channel.
VSENSE– B2 I Inverting voltage sense input.
VSENSE+ B3 I Non-inverting voltage sense input.
SW B4,B5 I/O Boost switch terminal.
AGND C1,C2 P Analog ground. Connect to low noise ground plane.
VREG C3 O High-side FET gate drive boost converter.
PGND C4,C5 P Power ground. Connect to high current ground plane.
VBAT D1 P Battery power supply. Connect to 3.0 V to 5.5 V battery supply.
AIN– D2 I Inverting analog input.
DIN D3 I Audio serial data input. Format is I2S, LJF, RJF, or TDM data.
ADDR D4 I I2C address select terminal. Set ADDR = GND for device 7-bit address 0x40; set ADDR = IOVDD for 7-bit address 0x41.
SDA D5 I/O I2C control bus data.
AVDD E1 P Analog low voltage supply terminal. Connect to 1.65 V to 1.95 V supply.
AIN+ E2 I Non-inverting analog input.
DOUT E3 O Serial I/V digital output. Format is I2S, LJF, RJF, TDM, or undecimated PDM data.
IVCLKIN E4 I Serial clock input for undecimated PDM I/V data.
SCL E5 I I2C control bus clock.
EN(1) F2 I Device enable (HIGH = Normal Operation, LOW = Standby)
WCLK F3 I Audio serial word clock.
BCLK F4 I Audio serial bit clock.
MCLK F5 I External master clock.
IOVDD F1 P Supply for digital input and output levels. Voltage range is 1.5 V to 3.6 V.
(1) Wait a minimum of 1ms after EN is pulled high or DEV_RESET is issued before accessing the control interface. EN=low will erase the TAS2552 device configuration. The TAS2552 device must be configured (see Initialization) after EN=high.​