SLASF31A December   2023  – October 2024 TAD5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Output Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 DAC Signal-Chain
        1. 6.3.6.1 Digital Interpolation Filters
          1. 6.3.6.1.1 Linear-phase filters
            1. 6.3.6.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.6.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.6.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.6.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.6.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.6.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.6.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.6.1.2 Low-latency Filters
            1. 6.3.6.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.6.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.6.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.6.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.6.1.2.5 Sampling Rate: 192kHz or 176.4kHz
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the DAC modulators and digital filter engine, as well as other control blocks.

In target mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 6-4 to Table 6-7 list the supported FSYNC and BCLK frequencies depending on IOVDD Supply.

Table 6-4 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies (IOVDD - 3.3V Operation)
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(8 kHz)		 FSYNC
(16 kHz)		 FSYNC
(24 kHz)		 FSYNC
(32 kHz)		 FSYNC
(48 kHz)		 FSYNC
(96 kHz)		 FSYNC
(192 kHz)
16 Reserved 0.256 0.384 0.512 0.768 1.536 3.072
24 Reserved 0.384 0.576 0.768 1.152 2.304 4.608
32 0.256 0.512 0.768 1.024 1.536 3.072 6.144
48 0.384 0.768 1.152 1.536 2.304 4.608 9.216
64 0.512 1.024 1.536 2.048 3.072 6.144 12.288
96 0.768 1.536 2.304 3.072 4.608 9.216 18.432
128 1.024 2.048 3.072 4.096 6.144 12.288 24.576
192 1.536 3.072 4.608 6.144 9.216 18.432 Reserved
256 2.048 4.096 6.144 8.192 12.288 24.576 Reserved
384 3.072 6.144 9.216 12.288 18.432 Reserved Reserved
512 4.096 8.192 12.288 16.384 24.576 Reserved Reserved
Table 6-5 Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies (IOVDD - 3.3V Operation)
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(7.35 kHz)		 FSYNC
(14.7 kHz)		 FSYNC
(22.05 kHz)		 FSYNC
(29.4 kHz)		 FSYNC
(44.1 kHz)		 FSYNC
(88.2 kHz)		 FSYNC
(176.4 kHz)
16 Reserved Reserved 0.3528 0.4704 0.7056 1.4112 2.8224
24 Reserved 0.3528 0.5292 0.7056 1.0584 2.1168 4.2336
32 Reserved 0.4704 0.7056 0.9408 1.4112 2.8224 5.6448
48 0.3528 0.7056 1.0584 1.4112 2.1168 4.2336 8.4672
64 0.4704 0.9408 1.4112 1.8816 2.8224 5.6448 11.2896
96 0.7056 1.4112 2.1168 2.8224 4.2336 8.4672 16.9344
128 0.9408 1.8816 2.8224 3.7632 5.6448 11.2896 22.5792
192 1.4112 2.8224 4.2336 5.6448 8.4672 16.9344 Reserved
256 1.8816 3.7632 5.6448 7.5264 11.2896 22.5792 Reserved
384 2.8224 5.6448 8.4672 11.2896 16.9344 Reserved Reserved
512 3.7632 7.5264 11.2896 15.0528 22.5792 Reserved Reserved
Table 6-6 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies (IOVDD - 1.8V Operation)
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(8 kHz)		 FSYNC
(16 kHz)		 FSYNC
(24 kHz)		 FSYNC
(32 kHz)		 FSYNC
(48 kHz)		 FSYNC
(96 kHz)		 FSYNC
(192 kHz)
16 Reserved 0.256 0.384 0.512 0.768 1.536 3.072
24 Reserved 0.384 0.576 0.768 1.152 2.304 4.608
32 0.256 0.512 0.768 1.024 1.536 3.072 6.144
48 0.384 0.768 1.152 1.536 2.304 4.608 9.216
64 0.512 1.024 1.536 2.048 3.072 6.144 12.288
96 0.768 1.536 2.304 3.072 4.608 9.216 Reserved
128 1.024 2.048 3.072 4.096 6.144 12.288 Reserved
192 1.536 3.072 4.608 6.144 9.216 Reserved Reserved
256 2.048 4.096 6.144 8.192 12.288 Reserved Reserved
384 3.072 6.144 9.216 12.288 Reserved Reserved Reserved
512 4.096 8.192 12.288 Reserved Reserved Reserved Reserved
Table 6-7 Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies (IOVDD - 1.8V Operation)
BCLK TO FSYNC RATIO BCLK (MHz)
FSYNC
(7.35 kHz)		 FSYNC
(14.7 kHz)		 FSYNC
(22.05 kHz)		 FSYNC
(29.4 kHz)		 FSYNC
(44.1 kHz)		 FSYNC
(88.2 kHz)		 FSYNC
(176.4 kHz)
16 Reserved Reserved 0.3528 0.4704 0.7056 1.4112 2.8224
24 Reserved 0.3528 0.5292 0.7056 1.0584 2.1168 4.2336
32 Reserved 0.4704 0.7056 0.9408 1.4112 2.8224 5.6448
48 0.3528 0.7056 1.0584 1.4112 2.1168 4.2336 8.4672
64 0.4704 0.9408 1.4112 1.8816 2.8224 5.6448 11.2896
96 0.7056 1.4112 2.1168 2.8224 4.2336 8.4672 Reserved
128 0.9408 1.8816 2.8224 3.7632 5.6448 11.2896 Reserved
192 1.4112 2.8224 4.2336 5.6448 8.4672 Reserved Reserved
256 1.8816 3.7632 5.6448 7.5264 11.2896 Reserved Reserved
384 2.8224 5.6448 8.4672 11.2896 Reserved Reserved Reserved
512 3.7632 7.5264 11.2896 Reserved Reserved Reserved Reserved

In the controller mode of operation, the device uses the MD3 pin, as the system clock, CCLK for the reference input clock source. In target mode of operation, the MD3 pin should be grounded.

The device provides flexibility in FSYNC selection with a supported system clock frequency option of either 256 × fS or 128 × fS or a fixed 48/44.1KSPS or 96/88.2KSPS as configured using the MD1 and MD2 pins.

The table Table 6-8 shows the FSYNC and BCLK selection for the controller mode using the MD1 and MD2 pins. In controller mode of operation, AVDD = 3.3V and Word-Length = 32.

Table 6-8 System Clock Selection for the Controller Mode
MD2 MD1 SYSTEM CLOCK SELECTION (Valid for Controller Mode only)
FSYNC I2S Mode TDM Mode
Low Low FSYNC = CCLK/256 BCLK = 64*fS For FSYNC<=48KSPS, BCLK = 256*fS, for 48KSPS<FSYNC<=96KSPS, BCLK = 128*fS, and for FSYNC>96KSPS, BCLK = 64*fS
Low High FSYNC = CCLK/128
High Low FSYNC = 96/88.2KSPS BCLK = 128*fS
High High FSYNC = 48/44.1KSPS BCLK = 256*fS
See Table 6-2 for the MD1 and MD2 pin function in the target mode of operation.