SLASF94A May 2024 – October 2024 MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228
PRODUCTION DATA
TI recommends connecting a combination of a 10µF and a 0.1µF low-ESR ceramic decoupling capacitor to the VDD and VSS pins. Higher-value capacitors may be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters).
The NRST reset pin is required to connect an external 47kΩ pullup resistor with a 10nF pulldown capacitor.
The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100kΩ resistor, populated between the ROSC pin and VSS, to stabilize the SYSOSC frequency by providing a precision reference current for the SYSOSC. This resistor needs to be 0.1% accurate and is not required if the SYSOSC FCL is not enabled.
For devices supporting external crystals, external bypass capacitors for the crystal oscillator pins are required. Refer to MSPM0 L-Series 32MHz Microcontrollers Technical Reference Manual which explains how to calculate the capacitor value.
A 0.47µF tank capacitor is required for the VCORE pin and needs to be placed close to the device with minimum distance to the device ground.
For 5V-tolerant open drain IOs (ODIO), a pullup resistor is required to output a logic high signal. This is required for I2C and UART functions if the ODIO are used.