SLAU320AJ July 2010 – May 2021
This step is only required for devices in which JTAG pins are shared with port I/Os, which is indicated by the presence of a TEST pin. This is the case on all devices that support the Spy-Bi-Wire protocol. Furthermore, some older device groups require special handling to enable 4-wire JTAG (see the "TEST Pin" column in Table 2-14).
Reference function: GetDevice, GetDevice_sbw, GetDevice_430X, GetDevice_430Xv2
To use the JTAG features of MSP430 devices with shared JTAG and a TEST pin, it is necessary to enable the shared JTAG pins for JTAG communication mode. Devices with dedicated JTAG inputs/outputs and no TEST pin do not require this step. The shared pins are enabled for JTAG communication by connecting the TEST pin to VCC. For normal operation (non-JTAG mode), this pin should be released, so that it is pulled to ground by the internal pulldown. Table 2-8 shows the port 1 pins that are used for JTAG communication.
Port 1 Function (TEST = Open) | JTAG Function (TEST = VCC) |
---|---|
P1.4 | TCK |
P1.5 | TMS |
P1.6 | TDI/TCLK |
P1.7 | TDO |
The SBW interface and any access to the JTAG interface is disabled while the TEST/SBWTCK pin is held low. This is accomplished by an internal pulldown resistor. The pin can also be tied low externally.
Pulling the TEST/SBWTCK pin high enables the SBW interface and disables the RST/NMI functionality of the RST/NMI/SBWTDIO pin. While the SBW interface is active, the internal reset signal is held high, and the internal NMI signal is held at the input value seen at RST/NMI with TEST/SBWTCK going high.
Devices with SBW also support the standard 4-wire interface. The 4-wire JTAG interface access is enabled by pulling the SBWTDIO line low and then applying a clock on SBWTCK. Exit the 4-wire JTAG mode by holding the TEST/SBWTCK low for more than 100 µs.
To select the 2-wire SBW mode, the SBWTDIO line is held high and the first clock is applied on SBWTCK. After this clock, the normal SBW timings are applied starting with the TMS slot, and the normal JTAG patterns can be applied, typically starting with the Tap Reset and Fuse Check sequence. Exit the SBW mode by holding the TEST/SBWTCK low for more than 100 µs.
In devices implementing the bootloader (BSL), the TEST/SBWTCK and RST/NMI/SBWTDIO are also used to invoke the BSL. Figure 2-13 shows different cases that are used to enter the SBW/JTAG or BSL mode.
On some Spy-Bi-Wire capable MSP430 devices, TEST/SBWTCK is very sensitive to rising signal edges that can cause the test logic to enter a state where an entry sequence (either 2-wire or 4-wire) is not recognized correctly and JTAG access stays disabled. Unintentional edges on SBWTCK can occur when the JTAG connector is connected to the target device. There are two possibilities to work around this problem and ensure a stable JTAG access initialization: