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34.2.1 12-Bit ADC Core
The ADC core converts an analog input to its 12-bit digital representation. The core uses two programmable and selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion. The digital output (NADC) is full scale (0FFFh) when the input signal is equal to or higher than VR+, and is zero when the input signal is equal to or lower than VR-. The input channel and the reference voltage levels (VR+ and VR-) are defined in the conversion-control memory.
Equation 13 shows the conversion formula for the ADC result NADC for single-ended mode.
Equation 14 shows the conversion formula for the ADC result NADC for differential mode.
Equation 15 describes the input voltage at which the ADC output saturates for singled-ended mode.
Equation 16 describes the input voltage at which the ADC output saturates for differential mode.
- VR– < Vin+ < VR+
- VR– < Vin– < VR+
where
Four control registers configure the ADC12_B core: ADC12CTL0, ADC12CTL1, ADC12CTL2, and ADC12CTL3. The ADC12ON bit enables or disables the core. The ADC12_B can be turned off when it is not in use to save power. If the ADC12ON bit is set to 0 during a conversion, the conversion is abruptly exited and the module is powered down. With few exceptions, an application can modify the ADC12_B control bits only when ADC12ENC = 0. ADC12ENC must be set to 1 before any conversion can take place.
The conversion results are always stored in binary unsigned format. For differential input, this means that an offset of 2048 is added to the result to make the number positive. The data format bit ADC12DF in ADC12CTL2 allows the user to read the conversion results as binary unsigned or signed binary (2s complement).