SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
ADC12_B Control 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | ADC12PDIV | ADC12SHSx | ADC12SHP | ADC12ISSH | |||
| r-0 | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADC12DIVx | ADC12SSELx | ADC12CONSEQx | ADC12BUSY | ||||
| rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-(0) |
| Can be modified only when ADC12ENC = 0. | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | Reserved | R | 0h |
Reserved. Always reads as 0. |
| 14-13 | ADC12PDIV | RW | 0h |
ADC12_B predivider. This bit predivides the selected ADC12_B clock source. 00b = Predivide by 1 01b = Predivide by 4 10b = Predivide by 32 11b = Predivide by 64 |
| 12-10 | ADC12SHSx | RW | 0h |
ADC12_B sample-and-hold source select 000b = ADC12SC bit 001b = see the device-specific data sheet for source 010b = see the device-specific data sheet for source 011b = see the device-specific data sheet for source 100b = see the device-specific data sheet for source 101b = see the device-specific data sheet for source 110b = see the device-specific data sheet for source 111b = see the device-specific data sheet for source |
| 9 | ADC12SHP | RW | 0h |
ADC12_B sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0b = SAMPCON signal is sourced from the sample-input signal. 1b = SAMPCON signal is sourced from the sampling timer. |
| 8 | ADC12ISSH | RW | 0h |
ADC12_B invert signal sample-and-hold. 0b = The sample-input signal is not inverted. 1b = The sample-input signal is inverted. |
| 7-5 | ADC12DIVx | RW | 0h |
ADC12_B clock divider 000b = /1 001b = /2 010b = /3 011b = /4 100b = /5 101b = /6 110b = /7 111b = /8 |
| 4-3 | ADC12SSELx | RW | 0h |
ADC12_B clock source select 00b = ADC12OSC (MODOSC) 01b = ACLK 10b = MCLK 11b = SMCLK |
| 2-1 | ADC12CONSEQx | RW | 0h |
ADC12_B conversion sequence mode select. This bit should only be modified when ADC12ENC = 0 except to stop a conversion immediately by setting ADC12CONSEQx = 00 when ADC12ENC = 1. 00b = Single-channel, single-conversion 01b = Sequence-of-channels 10b = Repeat-single-channel 11b = Repeat-sequence-of-channels |
| 0 | ADC12BUSY | R | 0h |
ADC12_B busy. This bit indicates an active sample or conversion operation. 0b = No operation is active. 1b = A sequence, sample, or conversion is active. |