SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
ADC12_B Interrupt Enable 2 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | |||||||
| r0 | r0 | r0 | r0 | r0 | r0 | r0 | r0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | ADC12RDYIE | ADC12TOVIE | ADC12OVIE | ADC12HIIE | ADC12LOIE | ADC12INIE | Reserved |
| r0 | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | Reserved | R | 0h |
Reserved. Always reads as 0. |
| 6 | ADC12RDYIE | RW | 0h |
ADC12_B local reference buffer ready interrupt enable. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 5 | ADC12TOVIE | RW | 0h |
ADC12_B conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 4 | ADC12OVIE | RW | 0h |
ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 3 | ADC12HIIE | RW | 0h |
Interrupt enable for the exceeding the upper limit interrupt of the window comparator for ADC12MEMx result register. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 2 | ADC12LOIE | RW | 0h |
Interrupt enable for the falling short of the lower limit interrupt of the window comparator for the ADC12MEMx result register. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 1 | ADC12INIE | RW | 0h |
Interrupt enable for the ADC12MEMx result register being greater than the ADC12LO threshold and below the ADC12HI threshold. The GIE bit must also be set to enable the interrupt. 0b = Interrupt disabled 1b = Interrupt enabled |
| 0 | Reserved | R | 0h |
Reserved. Always reads as 0. |