SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Comparator_E Control Register 1
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | CEMRVS | CEMRVL | CEON | CEPWRMD | |||
| r-0 | r-0 | r-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CEFDLY | CEEX | CESHORT | CEIES | CEF | CEOUTPOL | CEOUT | |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | Reserved | R | 0h | Reserved. Reads as 0. |
| 12 | CEMRVS | RW | 0h | This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.
0b = Comparator output state selects between VREF0 or VREF1. 1b = CEMRVL selects between VREF0 or VREF1. |
| 11 | CEMRVL | RW | 0h | This bit is valid of CEMRVS is set to 1.
0b = VREF0 is selected if CERS = 00, 01, or 10 1b = VREF1 is selected if CERS = 00, 01, or 10 |
| 10 | CEON | RW | 0h | On. This bit turns the comparator on. When the comparator is turned off the Comparator_E consumes no power.
0b = Off 1b = On |
| 9-8 | CEPWRMD | RW | 0h | Power mode
00b = High-speed mode 01b = Normal mode 10b = Ultra-low power mode 11b = Reserved |
| 7-6 | CEFDLY | RW | 0h | Filter delay. The filter delay can be selected in four steps. See the device-specific data sheet for details.
00b = Typical filter delay of approximately 450 ns 01b = Typical filter delay of approximately 900 ns 10b = Typical filter delay of approximately 1800 ns 11b = Typical filter delay of approximately 3600 ns |
| 5 | CEEX | RW | 0h | Exchange. This bit permutes the comparator 0 inputs and inverts the comparator 0 output.
0b = Exchange off 1b = Exchange on |
| 4 | CESHORT | RW | 0h | Input short. This bit shorts the + and – input terminals.
0b = Inputs not shorted 1b = Inputs shorted |
| 3 | CEIES | RW | 0h | Interrupt edge select for CEIIFG and CEIFG. Changing CEIES might set CEIFG.
0b = Rising edge for CEIFG, falling edge for CEIIFG 1b = Falling edge for CEIFG, rising edge for CEIIFG |
| 2 | CEF | RW | 0h | Output filter. Available if CEPWRMD = 00 or 01.
0b = Comparator_E output is not filtered 1b = Comparator_E output is filtered |
| 1 | CEOUTPOL | RW | 0h | Output polarity. This bit defines the CEOUT polarity.
0b = Noninverted 1b = Inverted |
| 0 | CEOUT | R | 0h | Output value. This bit reflects the value of the Comparator_E output. Writing this bit has no effect on the comparator output. |