SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
37.2.1.5 Comparator Input Selection And Output Bit Selection
The ESICA1X and ESISH bits within AFE1 select between the ESICIx channels and the ESICHx channels for the comparator input as described in Table 37-1.
The AFE2's ESICA2X bit selects either ESICIx channels (ESICA2X = 1) or the ESICHx channels (ESICA2X = 0) for the analog front-end AFE2.
Table 37-1 ESICAX and ESISH Input Selection
| ESICA1X | ESISH | Operation |
|---|---|---|
| 0 | 0 | ESICHx and excitation circuitry is selected within AFE1 |
| 0 | 1 | ESICHx and sample-and-hold circuitry is selected within AFE1 |
| 1 | X | ESICIx inputs are selected within AFE1 |
Note that the test insertion feature is only available for AFE1. The TESTDX signal and ESITESTS1(tsm) signal select between the ESIOUTx output bits and the ESITCHOUTx output bits for the comparator output as described in Table 37-2. TESTDX is controlled by the ESITESTD bit.
Table 37-2 Selected Output Bits
| TESTDX | ESICHx(tsm) | ESITESTS1(tsm) | Selected Output Bit |
|---|---|---|---|
| 0 | 00 | X | ESIOUT0 and ESIOUT4 |
| 0 | 01 | X | ESIOUT1 and ESIOUT5 |
| 0 | 10 | X | ESIOUT2 and ESIOUT6 |
| 0 | 11 | X | ESIOUT3 and ESIOUT7 |
| 1 | X | 0 | ESITCHOUT0 |
| 1 | X | 1 | ESITCHOUT1 |
When TESTDX = 0, the ESICHx(tsm) signals select which ESICIx or ESICHx channel is excited and connected to the comparator. The ESICHx(tsm) signals also select the corresponding output bit for the comparator result.
When TESTDX = 1, channel selection depends on the ESITESTS1(tsm) signal. When TESTDX = 1 and ESITESTS1(tsm) = 0, input channel selection is controlled with the ESITCH0x bits and the output bit is ESITCHOUT0. When TESTDX = 1 and ESITESTS1(tsm) = 1, input channel selection is controlled with the ESITCH1x bits and the output bit is ESITCHOUT1.
When AFE1's ESICA1X = 1, the ESICSEL and ESICI3 bits select between the ESICIx channels and the ESICI input, allowing storage of the comparator output for one input signal into the four output bits ESIOUT0 to ESIOUT3. This can be used to observe the envelope function of sensors.
The output logic is enabled by the ESIRSON(tsm) signal. When a comparator output is high while ESIRSON = 1, an internal latch is set. Otherwise the latch is reset. The latch output is written into the selected output bit with the rising edge of the ESISTOP(tsm) signal as shown in Figure 37-6.
Figure 37-6 Analog Front-End Output Timing