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22.2.4 Data Transfer Controller (DTC) and Internal Data Buffer
The SDHS supports output data rates up to 8 Msps, which is faster than the system DMA can support, so the SDHS has a dedicated Data Transfer Controller (DTC) and an internal data buffer to support up to 8-MHz data transfer speed to the target memory.
Figure 22-14 shows the block diagram of the output data path. A conversion result from digital filter goes first to the internal data buffer. The buffer has 64-word depth. As soon as a new data is available in the buffer, the data is latched with the system clock (called synchronization to the system clock) and is written to SDHSDT register. Then the DTC reads the data from SDHSDT register and transfers to the destination memory location.
The DTC may require more than one sample period to transfer the data to system memory. Thus, the buffer depth is selected to achieve the 8-MHz data transfer speed when the system clock is equal to or higher than the SDHS output data rate. Take care when selecting SDHSCTL1.OSR bits or the system clock frequency. The system clock frequency must be equal to or greater than the SDHS output data rate, or a data overflow may occur.
- System clock frequency ≥ SDHS output data rate
- SDHS output data rate = PLL output frequency / SDHSCTL1.OSR
The DTC is enabled by default but can be disabled when SDHSCTL2.DTCOFF = 1. When the DTC is disabled, the data in the SDHSDT register must be read by CPU. If the SDHSDT register has not been read by CPU over 64 sample periods, the internal buffer becomes full and does not take any more new data. In the case, newly generated data is lost and causes the overflow interrupt (SDHSRIS.OVF).
NOTE
If data conversion is performed with SDHSCTL2.DTCOFF = 1, the data buffer may not be empty when the conversion stops. The CPU can continue to read the data until the buffer is empty. While the CPU is reading the data from the buffer after conversion is stopped, data format configurations (SDHSCTL0.DFMSEL, SDHSCTL0.DALGN, and SDHSCTL0.OBR bits) must not be changed.
The destination system memory is the LEA RAM, which is part of system memory. The DTC automatically recognize the base address of the LEA RAM in the target device. Only offset address needs to be configured to SDHSDTCDA register.
- Destination address = LEA RAM base address + offset address
- Offset address = SDHSDTCDA register value x 2 (for example, if SDHSDTCDA = 2, then the destination address = LEA base address + 4)
The SDHSDTCCA register value automatically increases by 1 at every data transfer, so the current target address can be monitored by reading SDHSDTCDA register. The maximum offset address is 64KB. The SDHSDTCDA register value resets when the offset address reaches the 64KB limit and starts from zero again.
NOTE
The DTC block supports up to 64KB of memory size; however, the available memory (LEA RAM) could be smaller than 64KB (see the device-specific data sheet). If the SDHSDTCDA register goes beyond the available memory space, data transferred to the outside of the available memory is lost. In this case, the DTC block does not overwrite data in other memory areas, because it accesses only the LEA RAM.
Take care not to go beyond the available memory address range. The DTC cannot detect if the offset address goes beyond the available LEA RAM. TI recommends using SDHSCTL2.SMPSZ[9:0], which controls the total number of samples.
NOTE
While the DTC is transferring data to the destination memory, the memory is blocked from being accessed by CPU or DMA. If the CPU or DMA attempts to access the same memory, 0x3FFF is returned and an NMI is generated (DACCESSIFG).
Figure 22-15 Data Output Path