SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
DMA operation, meaning the implementation of the cipher modes Electronic code book (ECB), Cipher block chaining (CBC), Output feedback (OFB), and Cipher feedback (CFB) using the DMA, supports easy and fast encryption and decryption of more than 128 bits.
When DMA cipher mode support is enabled by setting the AESCMEN bit, the AES256 module triggers 'AES trigger 0', 'AES trigger 1', and 'AES trigger 2' (also called 'AES trigger 0-2') in a certain order to execute different block cipher modes together with the DMA module.
For example, when using ECB encryption with AESCMEN = 1, 'AES trigger 0' is triggered eight times for DMA word access to read out AESADOUT, and then 'AES trigger 1' is triggered eight times to fill the next data into AESADIN. Because the AES modules generates a trigger for each word or byte the single transfer mode of the DMA must be used.
Table 14-2 shows the behavior of the 'AES trigger 0-2' for the different cipher modes selected by AESCMx.
| AESCMx | AESOPx | 'AES trigger 0' | 'AES trigger 1' | 'AES trigger 2' |
|---|---|---|---|---|
| 00
ECB |
00
encryption |
Set after encryption ready, set again until 128 bit are read from AESADOUT | Set to load the first block and set after 'AES trigger 0' was served the last time, set again until 128 bit are written to AESADIN | not set |
| 01 or 11
decryption |
Set after decryption ready, set again until 128 bit are read from AESADOUT | Set to load the first block and set after 'AES trigger 0' was served the last time, set again until 128 bit are written to AESADIN | not set | |
| 01
CBC |
00
encryption |
Set after encryption ready, set again until 128 bit are read from AESADOUT | Set after 'AES trigger 0' was served the last time, set again until 128 bit are written to AESAXDIN | not set |
| 01 or 11
decryption |
Set after decryption ready, set again until 128 bit are written to from AESAXIN | Set after 'AES trigger 0' was served the last time, set again until 128 bit are read from AESADOUT | Set after 'AES trigger 1' was served the last time, set again until 128 bit are written to AESADIN | |
| 10
OFB |
00
encryption |
Set after encryption ready, set again until 128 bit are written to AESAXIN | Set after 'AES trigger 0' was served the last time, set again until 128 bit are read from AESADOUT | Set after 'AES trigger 1' was served the last time, set again until 128 bit are written to AESAXDIN |
| 01 or 11
decryption |
Set after decryption ready, set again until 128 bit are written to AESAXIN | Set after 'AES trigger 0' was served the last time, set again until 128 bit are read from AESADOUT | Set after 'AES trigger 1' was served the last time, set again until 128 bit are written to AESAXDIN | |
| 11
CFB |
00
encryption |
Set after encryption ready, set again until 128 bit are written to AESAXIN | Set after 'AES trigger 0' was served the last time, set again until 128 bit are read from AESADOUT | not set |
| 01 or 11
decryption |
Set after decryption ready, set again until 128 bit are written to AESAXIN | Set after 'AES trigger 0' was served the last time, set again until 128 bit are read from AESADOUT | Set after 'AES trigger 1' was served the last time, set again until 128 bit are written to AESADIN |
The retriggering of the 'AES trigger 0-2' until 128-bit of data are written or read from the corresponding register supports both byte and word access for writing and reading the state through the DMA.
For AESCMEN = 0, no DMA triggers are generated.
The following sections explain the configuration of the AES module for automatic cipher mode execution using DMA.
It is assumed that the key is written by software (or by a separate DMA transfer) before writing the first block to the AES state. The key shadow register always restores the original key, so that there is no need to reload it. The AESAKEY register should not be written after AESBLKCNTx is written to a non-zero value.
The number of blocks to be encrypted or decrypted must be programmed into the AESBLKCNTx bits before writing the first data. Writing a non-zero value into AESBLKCNTx starts the cipher mode sequence and, thus, AESBLKCNTx must be written after the DMA channels are configured.
Throughout these sections, the different DMA channels are called DMA_A, DMA_B, and so on. In the figures, these letters appear in dotted circles showing which operation is going to be executed by which DMA channel. The DMA counter must be loaded with a multiple of 8 for word mode or a multiple of 16 for byte mode and the single transfer mode of the DMA must be selected. The DMA priorities of DMA_A, DMA_B, and DMA_C do not play any role but static DMA priorities must be enabled. The DMA triggers must be configured as level-sensitive triggers.