SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions. The emulated instructions are listed in Table 4-7.
| Instruction | Explanation | Emulation | Status Bits(1) | |||
|---|---|---|---|---|---|---|
| V | N | Z | C | |||
| ADC(.B) dst | Add Carry to dst | ADDC(.B) #0,dst | * | * | * | * |
| BR dst | Branch indirectly dst | MOV dst,PC | – | – | – | – |
| CLR(.B) dst | Clear dst | MOV(.B) #0,dst | – | – | – | – |
| CLRC | Clear Carry bit | BIC #1,SR | – | – | – | 0 |
| CLRN | Clear Negative bit | BIC #4,SR | – | 0 | – | – |
| CLRZ | Clear Zero bit | BIC #2,SR | – | – | 0 | – |
| DADC(.B) dst | Add Carry to dst decimally | DADD(.B) #0,dst | * | * | * | * |
| DEC(.B) dst | Decrement dst by 1 | SUB(.B) #1,dst | * | * | * | * |
| DECD(.B) dst | Decrement dst by 2 | SUB(.B) #2,dst | * | * | * | * |
| DINT | Disable interrupt | BIC #8,SR | – | – | – | – |
| EINT | Enable interrupt | BIS #8,SR | – | – | – | – |
| INC(.B) dst | Increment dst by 1 | ADD(.B) #1,dst | * | * | * | * |
| INCD(.B) dst | Increment dst by 2 | ADD(.B) #2,dst | * | * | * | * |
| INV(.B) dst | Invert dst | XOR(.B) #–1,dst | * | * | * | * |
| NOP | No operation | MOV R3,R3 | – | – | – | – |
| POP dst | Pop operand from stack | MOV @SP+,dst | – | – | – | – |
| RET | Return from subroutine | MOV @SP+,PC | – | – | – | – |
| RLA(.B) dst | Shift left dst arithmetically | ADD(.B) dst,dst | * | * | * | * |
| RLC(.B) dst | Shift left dst logically through Carry | ADDC(.B) dst,dst | * | * | * | * |
| SBC(.B) dst | Subtract Carry from dst | SUBC(.B) #0,dst | * | * | * | * |
| SETC | Set Carry bit | BIS #1,SR | – | – | – | 1 |
| SETN | Set Negative bit | BIS #4,SR | – | 1 | – | – |
| SETZ | Set Zero bit | BIS #2,SR | – | – | 1 | – |
| TST(.B) dst | Test dst (compare with 0) | CMP(.B) #0,dst | 0 | * | * | 1 |