SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Timing State Machine Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | ESICLKAZSEL | ESITSMTRGx | ESISTART | ESITSMRP | ESIDIV3Bx | ||
r0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ESIDIV3Bx | ESIDIV3Ax | ESIDIV2x | ESIDIV1x | ||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
14 | ESICLKAZSEL | RW | 0h |
Control bit functionality selection. This bit allows to define the functionality of bit 5 in register ESITSMx. 0b = ESITSMx.5 bit is used as ESICLKON. See ESITSMx control register for further description. 1b = ESITSMx.5 bit is used as ESICAAZ. See ESITSMx control register for further description. |
13-12 | ESITSMTRGx | RW | 0h |
TSM start trigger selection. These bits allow to chose the source for the TSM start trigger. 00b = Halt mode. This setting allows to stop the TSM. 01b = TSM start trigger ACLK divider is used. ESIDIV3Ax and ESIDIV3Bx bits select the division rate for the TSM start trigger. 10b = Software trigger for TSM. When ESISTART bit is set by software a TSM start trigger is generated. Note that for this setting an ACLK synchronization sequence is performed that takes up to 2.5 ACLK cycles. 11b = Either the ACLK divider (ESIDIV3Ax and ESIDIV3Bx) or the ESISTART bit is used for TSM start trigger. |
11 | ESISTART | RW | 0h |
TSM software start trigger. In case the ESISTART bit is selected for TSM trigger generation this bit allows to generate a TSM start trigger by software. 0b = Idle state 1b = A TSM sequence is started. ESISTART is automatically cleared as soon as the TSM sequence starts. |
10 | ESITSMRP | RW | 0h |
TSM repeat mode 0b = Each TSM sequence is triggered by the ACLK divider controlled with the ESIDIV3Ax and ESIDIV3Bx bits or ESISTART control bit depending on ESITSMTRGx setting. 1b = Each TSM sequence is immediately started at the end of the previous sequence. |
9-7 | ESIDIV3Bx | RW | 0h |
TSM start trigger ACLK divider. These bits together with the ESIDIV3Ax bits select the division rate for the TSM start trigger. The division rate is shown in Table 37-25. The division rate can be calculated as: ((ESIDIV3A + 1) × 2 - 1) × ((ESIDIV3B + 1) × 2 - 1) × 2 |
6-4 | ESIDIV3Ax | RW | 0h |
TSM start trigger ACLK divider. These bits together with the ESIDIV3Bx bits select the division rate for the TSM start trigger. The division rate is shown in Table 37-25. The division rate can be calculated as: ((ESIDIV3A + 1) × 2 - 1) × ((ESIDIV3B + 1) × 2 - 1) × 2 |
3-2 | ESIDIV2x | RW | 0h |
ACLK divider. These bits select the ACLK division. 00b = /1 01b = /2 10b = /4 11b = /8 |
1-0 | ESIDIV1x | RW | 0h |
TSM SMCLK divider. These bits select the SMCLK division for the TSM. 00b = /1 01b = /2 10b = /4 11b = /8 |
ACLK Divider | ESIDIV3Bx | ESIDIV3Ax | ACLK Divider | ESIDIV3Bx | ESIDIV3Ax | |
---|---|---|---|---|---|---|
2 | 000 | 000 | 126 | 011 | 100 | |
6 | 000 | 001 | 130 | 010 | 110 | |
10 | 000 | 010 | 150 | 010 | 111 | |
14 | 000 | 011 | 154 | 011 | 101 | |
18 | 000 | 100 | 162 | 100 | 100 | |
22 | 000 | 101 | 182 | 011 | 110 | |
26 | 000 | 110 | 198 | 100 | 101 | |
30 | 000 | 111 | 210 | 011 | 111 | |
42 | 001 | 011 | 234 | 100 | 110 | |
50 | 010 | 010 | 242 | 101 | 101 | |
54 | 001 | 100 | 270 | 100 | 111 | |
66 | 001 | 101 | 286 | 101 | 110 | |
70 | 010 | 011 | 330 | 101 | 111 | |
78 | 001 | 110 | 338 | 110 | 110 | |
90 | 001 | 111 | 390 | 110 | 111 | |
98 | 011 | 011 | 450 | 111 | 111 | |
110 | 010 | 101 |