SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Timing State Machine Register
NOTE:
A TSM sequence should at least consist of three ESITSMx registers. For example, using ESITSM0 for idle state, ESITSM1 for measurement, and ESITSM2 as stop state; note that usually several ESITSMx registers are needed to perform a measurement.
While a TSM sequence is in progress the access to the ESITSMx registers is blocked. Reading the ESITSMx registers while a TSM sequence is in progress returns always a 0x0000.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ESIREPEATx | ESICLK | ESISTOP | ESIDAC | ||||
| rw | rw | rw | rw | rw | rw | rw | rw |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESITESTS1 | ESIRSON | ESICLKON ESICAAZ | ESICA | ESIEX | ESILCEN | ESICHx | |
| rw | rw | rw | rw | rw | rw | rw | rw |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | ESIREPEATx | RW | 0h |
These bits together with the ESICLK bit configure the duration of this state. ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1. Note that all ESIREPEATx bits should be cleared within the ESITSMx state that generates the end of sequence (ESISTOP bit is set). |
| 10 | ESICLK | RW | 0h |
This bit selects the clock source for the TSM. 0b = The TSM clock source is the high frequency source selected by the ESIHFSEL bit. 1b = The TSM clock source is ACLK |
| 9 | ESISTOP | RW | 0h |
This bit indicates the end of the TSM sequence. The duration of this state is always one high-frequency clock period, regardless of the ESICLK and ESIREPEATx settings. 0b = TSM sequence continues with next state 1b = End of TSM sequence |
| 8 | ESIDAC | RW | 0h |
TSM DAC on. This bit turns the AFE1 DAC and optionally also AFE2 DAC on. 0b = AFE1 DAC and AFE2 DAC are off during this state. 1b = AFE1 DAC is on during this state. AFE2 DAC is only on when ESIDAC2EN in ESIAFE control register is set. |
| 7 | ESITESTS1 | RW | 0h |
TSM test cycle control. This bit selects for this state which channel-control bits and which DAC registers are used for a test cycle. 0b = The ESITCH0x bits select the channel and ESIDACR6 is used for the DAC 1b = The ESITCH1x bits select the channel and ESIDACR7 is used for the DAC |
| 6 | ESIRSON | RW | 0h |
Internal output latches enabled. This bit enables the internal latches of the AFE output stage. 0b = Output latches disabled 1b = Output latches enabled |
| 5 | ESICLKON ESICAAZ | RW | 0h |
This control bit in the ESITSMx control register can either be used as ESICLKON bit or ESICAAZ bit. Its functionality is selectable by the control bit CLKCAAZSEL in register TSM. ESITSM.ESICLKAZSEL=0 → ESICLKON: High-frequency clock on. Setting this bit turns the high-frequency clock source on for this state when ESICLK = 1, even though the high frequency clock is not used for the TSM. When the . high-frequency clock is sourced from the DCO, the DCO is forced on for this state, regardless of the MSP430 low-power mode. 0b = High-frequency clock is off for this state when ESICLK = 1 1b = High-frequency clock is on for this state when ESICLK = 1 ESITSM.ESICLKAZSEL=1 → ESICAAZ: Comparator Offset cancellation by doing an autozero cycle. 0b = "AZ-compensation Compare phase", Comparator compares (this phase must be preceded by the "AZ-compensation Auto Zero Phase" for each compare). 1b = "AZ-compensation Auto Zero phase", Comparator Offset cancellation sequence is active (autozero). The length for autozero is adjusted by the selected clock (ESICLK) and the programmed repeat cycles (ESIREPEATx). See device-specific data sheet for appropriate timing requirements. |
| 4 | ESICA | RW | 0h |
TSM comparator on. Setting this bit turns the AFE1 comparator and optionally the AFE2 comparator on for this state. 0b = AFE1 comparator and AFE2 comparator are off during this state 1b = AFE1 comparator is on during this state. AFE2 comparator is only on when ESICA2EN in ESIAFE control register is set. |
| 3 | ESIEX | RW | 0h |
Excitation and sample-and-hold. This bit, together with the ESISH and ESITEN bits, enables the excitation transistor or samples the input voltage during this state. ESILCEN must be set to 1 when ESIEX = 1. 0b = Excitation transistor disabled when ESISH = 0 and ESITEN = 1. Sampling disabled when ESISH = 1 and ESITEN = 0. 1b = Excitation transistor enabled when ESISH = 0 and ESITEN = 1. Sampling enabled when ESISH = 1 and ESITEN = 0. |
| 2 | ESILCEN | RW | 0h |
LC enable. Setting this bit turns the damping transistor off, enabling the LC oscillations during this state when ESITEN = 1. 0b = All ESICHx channels are internally damped. No LC oscillations. 1b = The selected ESICHx channel is not internally damped; the LC oscillates. All other unselected ESICHx channels are internally damped (no LC oscillations). |
| 1-0 | ESICHx | RW | 0h |
Input channel select. These bits select the input channel to be measured or excited during this state. 00b = ESICH0 01b = ESICH1 10b = ESICH2 11b = ESICH3 |