SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
8.4 FRAM Power Control
To achieve maximum power efficiency of FRAM operations, the FRAM controller A (FRCTL_A) supports a power control mode. There are three inputs that influence the power state of FRAM: the FRPWR bit, FRAM access (read or write), and the device power mode.
Table 8-2 summarizes how FRAM power modes are controlled by the source. Figure 8-2 shows the flow of FRAM power mode transitions.
While the device is in active mode(AM), FRAM power is controlled by the FRPWR bit and FRAM access. When the FRPWR is set, FRAM goes to ACTIVE mode regardless of FRAM access. When the FRPWR is cleared by the CPU and there is no access to FRAM, the FRAM goes into INACTIVE mode so that the FRAM does not consume power.
INACTIVE mode can be used if FRAM access is not required for a significant amount of time. For example, short tasks can be executed from RAM, so while CPU runs from RAM, FRAM can be powered off. When the FRAM is in the INACTIVE mode, wake-up is automatic. An access to FRAM (read or write) wakes up the FRAM before performing the access. In this case, the FRPWR bit is set automatically by the FRAM controller A (FRCTL_A).
Care must be taken when using the FRPWR bit. When the FRAM is powered off, there is a wake-up time delay before the FRAM can be accessed again. The delay should be considered to avoid affecting system performance. See the device data sheet for the delay time.
When the device enters LPM0, LPM1, LPM2, LPM3, or LPM4, the FRAM also enters INACTIVE mode regardless of FRPWR bit status, however FRPWR bit determines the power status when the device wakes up from a LPM. When the device wakes up from a low-power mode to active mode (AM), FRAM Controller A (FRCTL_A) immediately wakes up FRAM memory if the FRPWR is set. If the FRPWR bit is cleared, FRAM memory remains in INACTIVE mode until an access to FRAM occurs (read or write). The latter case can be used to reduce the device power consumption if the device wakes up only for a short amount of time, and the task during device active mode can be executed from RAM with no need to access FRAM memory. See Table 8-2 and Figure 8-2 for details.
Table 8-2 FRAM Power Mode Transition
| Power Control Source | FRAM Power State (Start) | FRAM Power State (End) | ||
|---|---|---|---|---|
| Device Power Mode | FRPWR Bit | FRAM Access | ||
| AM | 1 (after PUC) | Don't care | ACTIVE | ACTIVE |
| AM | 1 → 0 | No | ACTIVE | INACTIVE |
| AM | 0 | No → Yes | INACTIVE | ACTIVE (FRPWR bit is set automatically) |
| AM | 0 →1 | No | INACTIVE | ACTIVE |
| AM → LPM0, LPM1, LPM2, LPM3, or LPM4 | Don't care | No | Don't care | INACTIVE |
| LPM0 | Don't care | No → Yes | Don't care | ACTIVE (FRPWR bit is set automatically) |
| LPM0, LPM1, LPM2, LPM3, or LPM4 → AM | 1 | No | INACTIVE | ACTIVE |
| LPM0, LPM1, LPM2, LPM3, or LPM4 → AM | 0 | No | INACTIVE | INACTIVE |
Figure 8-2 shows the flow of the FRAM power transitions.
Figure 8-2 FRAM Power Control Diagram