SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
21.3.3 Input Channels (CH0_IN and CH1_IN)
Figure 21-13 shows the functional block diagram for the input channels, CH0_IN and CH1_IN.
Figure 21-13 SAPH or SAPH_A Analog Input Signal Chain The PGA uses only one input channel at a time, and the input channel is selected by SAPHICTL0.MUXSEL when SAPHICTL0.MUXCTL = 0 and SAPHMCNF.LPBE = 0 (register mode) or by the acquisition sequencer (ASQ) when SAPHICTL0.MUXCTL = 1 and SAPHMCNF.LPBE = 0 (auto mode). Register mode uses the SAPHOCTL0, SAPHOCTL1, SAPHOSEL, and SAPHBCTL regiters to control the signal chain. Auto mode uses the SAPHASCTL0, SAPHASCTL1, SAPHAPOL, SAPHAPLEV and SAPHAHIZ registers to control the signal chain.
In Ultra Low Power Bias mode (SAPHMCNF=1) both register sets are and the multiplexer selection is controlled by the ASQ.
The PGA has two input channels, but one of the channels is a dummy input, which has the same input impedance of the real input. The dummy input is designed to meet the impedance match requirement between transmit mode and receive mode of one channel. The dummy impedance is enabled when SAPHICTL0.DUMEN = 1 (default).
The input multiplexer is powered by a charge pump, which generates 3.2 V from the USS LDO voltage (1.6 V). The charge pump is turned on while the SAPHMCNF.CPEO=1 and during the preparation/arming for SDHS acquisition. If desired, the charge pump is turned off while capturing the Rx signal through the SDHS to reduce noise (SAPHBCTL.CPDA = 0); however, if signal capture is more than 300 µs, the charge pump should remain on (SAPHBCTL.CPDA = 1). Configure SAPHBCTL.CPDA before starting a measurement sequence. The clock of the charge pump is generated from a divided SDHS modulator frequency to maintain coherence during acquisition.
The impedance of the bias voltages TxBias and RxBias can be programmed with SAPHMCNF.BIMP .This allows to find the best fit for the reactant behavior of transducers on bias voltage changes (shorter ringing).
Table 21-2 Supply to the Rx Multiplexer
| Register | Description | Recommended Data Capture Time (Typical) |
|---|---|---|
| SAPHBCTL.CPDA = 0 (default) | The charge pump is automatically off when data capture begins. | <300 µs |
| SAPHBCTL.CPDA = 1 | The charge pump remains on during data capture. | ≥300 µs |