SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
9.2.1 Main Memory Segments
The MPU can logically divide the main memory into three segments. The size of each segment is defined by setting the borders between adjacent segments. To configure three segments, a lower border (B1) and a higher border (B2) are positioned by control register bits MPUSEGB1[15:0] and MPUSEGB2[15:0], respectively, in the MPUSEGBx registers. The position of both borders is limited to the 16 most significant bits of the memory address space (20-bit). Therefore, the segment borders registers are equivalent to the memory address bus, shifted right by 4 bits (see Figure 9-2).
Table 9-1 shows the minimum segment size. Depending on the total memory size, some of the border register bits must be written as zero. Table 9-1 summarizes the user-selectable bits and fixed bits for different memory sizes (see the device-specific data sheet for total memory size). Figure 9-3 and Figure 9-4 show fixed bits of the segment register when memory size is 128KB and 256KB respectively.
The beginning of segment 1 is the lowest available address for the main memory as defined in the device-specific data sheet. The lower border (B1) defines the end of segment 1 and the beginning of segment 2. The higher border (B2) defines the end of segment 2 and beginning of segment 3. The end of segment 3 is the highest main memory address as defined in the device-specific data sheet. For example, devices with up to 64KB of FRAM, the highest memory address is 013FFFh. Segment 2 includes the address defined by the lower border (B1) but excludes the higher border (B2).
The address bus (MAB) is analyzed by the MPU using the 16 most significant bits along with the current border settings.
- If the significant address bits are lower than MPUSEGB1[15:0], segment 1 is selected.
- If the significant address bits are equal to or greater than MPUSEGB1[15:0] and less than MPUSEGB2[15:0], segment 2 is selected.
- If the significant address bits are equal to or greater than MPUSEGB2[15:0], segment 3 is selected.
Figure 9-2 Segment Border Register Table 9-1 Address Comparator Bit Selection
| FRAM Size | Index of Used MSB Address Bus (n) | User-Selectable Border Register Bits | Fixed Border Register Bits (zero) | Segment Size
(bytes) |
|---|---|---|---|---|
| 32KB < size ≤ 128KB | 17-bit | [13:6] | [15:14] and [5:0] | 1k |
| 128KB < size ≤ 256KB | 18-bit | [14:6] | [15] and [5:0] | 1k |
Figure 9-3 Example of Segment Border Register Fixed Bits When FRAM Size = 128KB 
Figure 9-4 Example of Segment Border Register Fixed Bits When FRAM Size = 256KB NOTE
The same result is calculated during MAB analysis of segment membership independent of whether the higher value is in MPUSEGB1[15:0] or MPUSEGB2[15:0]. If MPUSEGB1[15:0] = MPUSEGB2[15:0], Segment 2 is not available and the main memory only contains 2 segments.
Figure 9-5 shows an example segmentation of the main memory.
Figure 9-5 Segmentation of Main Memory