SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
1.4 Operating Modes
The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 1-5.
The operating modes take into account three different needs:
- Ultra-low power
- Speed and data throughput
- Minimization of individual peripheral current consumption
The low-power modes LPM0 through LPM4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the SR. The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the SR is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine. When setting any of the mode-control bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled clock are disabled until the clock becomes active. Peripherals may also be disabled with their individual control register settings. All I/O port pins, RAM, and registers are unchanged. Wakeup from LPM0 through LPM4 is possible through all enabled interrupts.
When LPMx.5 (LPM3.5 or LPM4.5) is entered, the voltage regulator of the Power Management Module (PMM) is disabled. All RAM and register contents are lost. Although the I/O register contents are lost, the I/O pin states are locked upon LPMx.5 entry. See the Digital I/O chapter for further details. Wakeup from LPM4.5 is possible through a power sequence, a RST event, or from specific I/O. Wakeup from LPM3.5 is possible through a power sequence, a RST event, RTC event, or from specific I/O.
NOTE
The TEST/SBWTCK pin is used to enable the connection of external development tools with the device through Spy-Bi-Wire or JTAG debug protocols. The connection is usually enabled when the TEST/SBWTCK is high. When the connection is enabled the device enters a debug mode. In the debug mode the entry and wake-up times to and from low power modes may be different compared to normal operation. Pay careful attention to the real-time behavior when using low power modes with the device connected to a development tool!
See the EEM chapter for further details.
Table 1-2 Operation Modes
| SCG1(2) | SCG0 | OSCOFF(2) | CPUOFF(2) | Mode | CPU and Clocks Status(1) |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Active | CPU, MCLK are active. |
| ACLK is active. SMCLK optionally active (SMCLKOFF = 0). | |||||
| DCO is enabled if sources ACLK, MCLK, or SMCLK (SMCLKOFF = 0). | |||||
| DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). | |||||
| 0 | 0 | 0 | 1 | LPM0 | CPU, MCLK are disabled. |
| ACLK is active. SMCLK optionally active (SMCLKOFF = 0). | |||||
| DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0). | |||||
| DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). | |||||
| 0 | 1 | 0 | 1 | LPM1 | CPU, MCLK are disabled. |
| ACLK is active. SMCLK optionally active (SMCLKOFF = 0). | |||||
| DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0). | |||||
| DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). | |||||
| 1 | 0 | 0 | 1 | LPM2 | CPU, MCLK are disabled. |
| ACLK is active. SMCLK is disabled. | |||||
| 1 | 1 | 0 | 1 | LPM3 | CPU, MCLK are disabled. |
| ACLK is active. SMCLK is disabled. | |||||
| 1 | 1 | 1 | 1 | LPM4 | CPU and all clocks are disabled. |
| 1 | 1 | 1 | 1 | LPM3.5 | When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, RTC operation is possible when configured properly. See the RTC module for further details. |
| 1 | 1 | 1 | 1 | LPM4.5 | When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, all clock sources are disabled; that is, no RTC operation is possible. |