SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The ESI's comparator has an offset that drifts over temperature and supply voltage. For some applications the specified offset error and offset drift may be acceptable - see device-specific data sheet. If the offset error is not acceptable, adding a comparator autozero cycle within the TSM sequence can minimize the offset error. After the inserted autozero TSM cycle, the comparator operates effectively with a zeroed offset.
Adding an ESITSMx state within the TSM sequence, which has the ESICAAZ bit selected (ESITSM.ESICLKAZSEL=1) and set, performs the comparator autozeroing. As long as the ESICAAZ bit is set the autozeroing is performed. This means, the length of the appropriate ESITSMx state defines the length of autozeroing. The following code excerpt shows how to include an autozeroing cycle within a TSM sequence. The example focus on ESICA and ESICAAZ control bits:
...
ESITSM5 = TSM_State5; // TSM_State5 is a placeholder for any setting;
// Comparator is disabled (ESICA=0, ESICAAZ=0)
ESITSM6 = ESICA + ESICAAZ + Length + TSM_State6;
// comparator is switched on and at the same time the autozeroing is
// performed. Length is defined by ESCLK and ESIREPEATx bits -
// appropriate setting needed to meet autozeroing timing requirements;
// see device-specific data sheet (ESICA=1, ESICAAZ=1)
ESITSM7 = ESICA + TSM_State7;
// normal comparator operation: settle comparator
// (ESICA=1, ESICAAZ=0)
ESITSM8 = ESICA + TSM_State8;
// normal comparator operation: processing of comparator output signal
// (ESICA=1, ESICAAZ=0)
...