SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
21.3.1 Output Channels (CH0_OUT and CH1_OUT)
Figure 21-12 shows the functional block diagram for the output channels, CH0_OUT and CH1_OUT.
Figure 21-12 PHY Output Pins The output pins (CH0_OUT and CH1_OUT) can be used as general I/O pins when SAPHOSEL.PCH0SEL = 0 or 3. In this case, the polarity of the two pins is controlled by SAPHOCTL0.CH0OUT and SAPHOCTL0.CH1OUT, and the pins are enabled or disabled (Hi-Z) by SAPHOCTL0.CH0OE and SAPHOCTL0.CH1OE. The pins can be connected to GND through the SWG0 and SWG1 switches by SAPHOCTL0.CH0TERM and SAPHOCTL0.CH1TERM, respectively.
When SAPHOSEL.PCH0SEL = 1, the output pins work as single output drivers. The pulses generated by PPG are output on the selected pin. This is the typical use case for the flow measurement application.
When SAPHOSEL.PCH0SEL = 2, the two output pins working as differential output drivers. The pulses generated by PPG are output on both pins differentially.
When SAPHOSEL.PCH0SEL = 1 or 2, the two pins are controlled by the PPG block and ASQ block. The pins are automatically enabled when PPG generates pulses. The SWG0 and SWG1 switches are controlled by ASQ as part of measurement sequence (see Section 21.4).
The drive strength of DRV0 and DRV1 are maximized when SAPHOCTL1.CH0FP = 1 and SAPHOCTL1.CH1FP = 1, respectively. The drive strength of the pins are determined by SAPHCH0PUT, SAPHCH0PDT, SAPHCH1PUT, and SAPHCH1PDT when SAPHOCTL1.CH0FP = 0 and SAPHOCTL1.CH1FP = 0, respectively (see Section 21.3.2).
When SAPHOSEL.PCH0SEL = 1 or 2, the two pins are controlled by the PPG block and ASQ block. The pins are automatically enabled when PPG generates pulses. The SWG0 and SWG1 switches are controlled by ASQ as part of measurement sequence (see Section 21.4).