SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The following software example shows the recommended use of and the handling overhead. The P1IV value is added to the PC to automatically jump to the appropriate routine. The code to handle any other PxIV register is similar.
The numbers at the right margin show the number of CPU cycles that are required for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles but not the task handling itself.
;Interrupt handler for P1 Cycles
P1_HND ... ; Interrupt latency 6
ADD &P1IV,PC ; Add offset to Jump table 3
RETI ; Vector 0: No interrupt 5
JMP P1_0_HND ; Vector 2: Port 1 bit 0 2
JMP P1_1_HND ; Vector 4: Port 1 bit 1 2
JMP P1_2_HND ; Vector 6: Port 1 bit 2 2
JMP P1_3_HND ; Vector 8: Port 1 bit 3 2
JMP P1_4_HND ; Vector 10: Port 1 bit 4 2
JMP P1_5_HND ; Vector 12: Port 1 bit 5 2
JMP P1_6_HND ; Vector 14: Port 1 bit 6 2
JMP P1_7_HND ; Vector 16: Port 1 bit 7 2
P1_7_HND ; Vector 16: Port 1 bit 7
... ; Task starts here
RETI ; Back to main program 5
P1_6_HND ; Vector 14: Port 1 bit 6
... ; Task starts here
RETI ; Back to main program 5
P1_5_HND ; Vector 12: Port 1 bit 5
... ; Task starts here
RETI ; Back to main program 5
P1_4_HND ; Vector 10: Port 1 bit 4
... ; Task starts here
RETI ; Back to main program 5
P1_3_HND ; Vector 8: Port 1 bit 3
... ; Task starts here
RETI ; Back to main program 5
P1_2_HND ; Vector 6: Port 1 bit 2
... ; Task starts here
RETI ; Back to main program 5
P1_1_HND ; Vector 4: Port 1 bit 1
... ; Task starts here
RETI ; Back to main program 5
P1_0_HND ; Vector 2: Port 1 bit 0
... ; Task starts here
RETI ; Back to main program 5