SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The PSM has three 16-bit counters ESICNT0, ESICNT1, and ESICNT2. ESICNT0 is updated with Q1, ESICNT1 is updated with Q1 and Q2, and ESICNT2 is updated with Q2. The counters can be read from the ESICNT0, ESICNT1, and ESICNT2 registers. The different counters can individually be reset by setting the ESICNTxRST control bits. When ESIEN = 0, all counters are held in reset.
ESICNT0 increments based on Q1. When ESICNT0EN = 1, ESICNT0 increments on a transition to a state where bit Q1 is set.
ESICNT1 can increment or decrement based on Q1 and Q2. When ESICNT1EN = 1, ESICNT1 decrements on a transition to a state where bit Q2 is set and it increments on a transition to a state where bit Q1 is set. In case both bits Q1 and Q2 are set on a state transition, ESICNT1 does not increment or decrement.
ESICNT2 decrements based on Q2. When ESICNT2EN = 1, ESICNT2 decrements on a transition to a state where bit Q2 is set. On the first count after a reset ESICNT2 will roll over from zero to 65535 (0FFFFh).
When the next state is calculated to be the same state as the current state, the counters ESICNT0, ESICNT1, and ESICNT2 are incremented or decremented according to Q1 and Q2 at the state transition. For example, if the current state is 05h and Q2 is set, and if the next state is calculated to be 05h, the transition from state 05h to 05h will decrement ESICNT2 if ESICNT2EN = 1.
NOTE
A read from any ESICNTx register should occur while PSM counters are not triggered. This can be realized by reading the ESI counters in the ESIIFG1 interrupt service routine and choosing appropriate timing of TSM sequences. Alternatively, the ESI counters may be read multiple times, and a majority vote taken in software to determine the correct reading.